POWER6
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Out-of-order execution
Robert Tomasulo
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Loop optimization
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POWER4
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Loongson
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OOO
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Microarchitecture
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AMD Am29000
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HAL SPARC64
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Dataflow architecture
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Pipeline (computing)
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POWER1
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Instruction scheduling
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Branch (computer science)
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Metaflow Technologies
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HAL Computer Systems
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Von Neumann programming languages
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AMD K5
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CPU cache
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Addressing mode
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Lynn Conway
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Memory barrier
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List of x86 instructions
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PowerPC G4
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Stack machine
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Register renaming
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Metaprogramming
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Tomasulo's algorithm
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Hazard (computer architecture)
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Re-order buffer
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Delay slot
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Speculative execution
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VIA C3
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Instruction-level parallelism
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Spinlock
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Clock rate
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Program optimization
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Instruction pipelining
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Predication (computer architecture)
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Pentium Pro
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Hyper-threading
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Parallel computing
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Program counter
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Superscalar processor
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Very long instruction word
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List of computing and IT abbreviations
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Optimizing compiler
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Floating-point unit
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Mutual exclusion
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X86
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Decoupled architecture
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Out of Order execution
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Out of order execution
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Decoupled Architecture
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