In computer science, instruction scheduling is a compiler optimization used to improve instruction-level parallelism, which improves performance on machines with instruction pipelines. Put more simply, it tries to do the following without changing the meaning of the code:
- Avoid pipeline stalls by rearranging the order of instructions.
Until version 12.0.0, the instruction scheduling in LLVM/Clang could only accept a (called in LLVM parlance) switch for both instruction set and scheduling. Version 12 adds support for () for x86 only.
Sources of information on latency and port usage include:
- GCC and LLVM;
- Agner Fog, who compiles extensive data for the x86 architecture;
- InstLatx64, which uses AIDA64 to collect data on x86 CPUs.
- uops.info, which provides latency, throughput, and port usage information for x86 microarchitectures.
LLVM's should be usable on all machines, especially to gather information on non-x86 ones.
See also
- Branch predication
- Code generation
- Instruction unit
- Out-of-order execution
References
</references>
Further reading
- (Trace scheduling)
- (Percolation scheduling)
- (Global scheduling)