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The System Management Bus (SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in chipsets of computer motherboards for communication with the power source for ON/OFF instructions. The exact functionality and hardware interfaces vary with vendors.

It is derived from I²C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery System and ACPI). Other devices might include external master hosts, temperature sensor, fan or voltage sensors, lid switches, clock generator, and RGB lighting. Peripheral Component Interconnect (PCI) add-in cards may connect to an SMBus segment.

A device can provide manufacturer information, indicate its model/part number, save its state for a suspend event, report different types of errors, accept control parameters, return status over SMBus, and poll chipset registers. The SMBus is generally not user configurable or accessible. It carries clock, data, and instructions and is based on Philips' I²C serial bus protocol.

Electrical

Input Voltage (V<sub>IL</sub> and V<sub>IH</sub>)

When mixing devices, the I²C specification defines the input levels to be 30% and 70% of the supply voltage V<sub>DD</sub>, which may be 5&nbsp;V, 3.3&nbsp;V, or any other value. Instead of relating the bus input levels to V<sub>DD</sub>, SMBus defines them to be fixed. SMBus 2.0 defines V<sub>IL,max</sub> at 0.8&nbsp;V and V<sub>IH,min</sub> at 2.1&nbsp;V, and supports a V<sub>DD</sub> ranging from 3 to 5&nbsp;V, while in SMBus 3.0, the levels are defined at 0.8 and 1.35&nbsp;V, with a V<sub>DD</sub> ranging from 1.8 to 5&nbsp;V.

SMBALERT#

The SMBus has an extra optional shared interrupt signal called SMBALERT#, which can be used by slaves to tell the host to ask its slaves about events of interest.

SMBus also defines a less common "Host Notify Protocol", providing similar notifications but passing more data and building on the I²C multi-master mode.

Support

SMBus devices are supported by FreeBSD, OpenBSD, NetBSD, DragonFly BSD, Linux, Windows 98 and newer and Windows CE.

Replacement

DDR5 introduces I3C for its presence detect communication, replacing SMBus.

PCI express devices commonly use SMBus as a "out-of-band management port". However, device vendors frequently use SMBus multiplexers (Mux) to manage address clashes (which are in turn caused by them not implementing the Address Resolution Protocol), causing link interruptions that break Management Component Transport Protocol and other protocols when the Mux switches targets. To solve this problem, SNIA's Enterprise and Data Center Standard Form Factor version 3.1 (January 2023) describes a way to use I3C basic over the PCIe two-wire interface. NVM Express 2.1 (August 2024) is also reworded to allow the use of I3C, "to match the new conventions used by SNIA SFF TA's EDSFF and PCI-SIG specifications for I3C".

See also

  • List of network buses
  • Embedded controller (EC)
  • Super I/O
  • Low Pin Count (LPC)
  • Serial Peripheral Interface (SPI)
  • Platform Environment Control Interface (PECI)
  • Host Embedded Controller Interface (HECI)
  • Power Management Bus (PMBus)
  • System Management Controller (SMC)

References

  • Official SMBus specifications (free)
  • SBS forum
  • SMBus at tech-faq.com