Motorola 68000 series

The Motorola 68000 series (also known as 680x0, m68000, m68k, or 68k) is a family of 32-bit complex instruction set computer (CISC) microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and were the primary competitors of Intel's x86 microprocessors. They were best known as the processors used in the early Apple Macintosh, the Sharp X68000, the Commodore Amiga, the Sinclair QL, the Atari ST and Falcon, the Atari Jaguar, the Sega Genesis (Mega Drive) and Sega CD, the Philips CD-i, the Capcom System I (Arcade), the AT&T UNIX PC, the Tandy Model 16/16B/6000, the Sun Microsystems Sun-1, Sun-2 and Sun-3, the NeXT Computer, NeXTcube, NeXTstation, and NeXTcube Turbo, early Silicon Graphics IRIS workstations, the Aesthedes, computers from MASSCOMP, the Texas Instruments TI-89/TI-92 calculators, the Palm Pilot (all models running Palm OS 4.x or earlier), the Control Data Corporation CDCNET Device Interface, the VTech Precomputer Unlimited and the Space Shuttle. Although no modern desktop computers are based on processors in the 680x0 series, derivative processors are still widely used in embedded systems.

Motorola ceased development of the 680x0 series architecture in 1994, replacing it with the PowerPC RISC architecture, which was developed in conjunction with IBM and Apple Computer as part of the AIM alliance.

Family members

Generation one (internally 16/32-bit, and produced with 8-, 16-, and 32-bit interfaces)
68000
68EC000
68SEC000
68HC000
68008
68010
68012
Generation two (internally fully 32-bit)
68020
68EC020
68030
68EC030
Generation three (pipelined)
68040
68EC040
68LC040
Generation four (superscalar)
68060
68EC060
68LC060
Others
Freescale 683XX (CPU32 aka 68330, 68360 aka QUICC)
Freescale ColdFire
Freescale DragonBall
Philips 68070
APOLLO CORE 68080

Improvement history

68010:

Virtual memory support (restartable instructions)
'Loop mode' for faster string and memory library primitives
Multiply instruction uses 14 fewer clock ticks
2 GiB directly accessible memory (68012 variant)

68020:

32-bit address & arithmetic logic unit (ALU)
Three stage pipeline
Instruction cache of 256 bytes
Unrestricted word and longword data access (see alignment)
8× multiprocessing ability
Larger multiply (32×32 → 64 bits) and divide (64÷32 → 32 bits quotient and 32 bits remainder) instructions, and bit field manipulations
Addressing modes added scaled indexing and another level of indirection
Low cost, EC = 24-bit address

68030:

Split instruction and data cache of 256 bytes each
On-chip memory management unit (MMU) (68851)
Low cost EC = No MMU
Burst Memory Interface

68040:

Instruction and data caches of 4 KB each
Six stage pipeline
On-chip floating-point unit (FPU)
FPU lacks IEEE transcendental function ability
FPU emulation works with 2E71M and later chip revisions
Low cost LC = No FPU
Low cost EC = No FPU or MMU

68060:

Instruction and data caches of 8 KB each
10 stage pipeline
Two cycle integer multiplication unit
Branch prediction
Dual instruction pipeline
Instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU
Low cost LC = No FPU
Low cost EC = No FPU or MMU

Feature map

{| class="wikitable"

! Year !! CPU !! Package !! Frequency (max) [in MHz] !! Address bus bits !! MMU !! FPU

| 1979 || 68000 || , , , , , , || 8–50 || 24 || - || -

| 1982 || 68008 || , || 8–16.67 || 20 or 22 || - || -

| 1982 || 68010 || , , || || 24 || 68451 || -

| 1982 || 68012 || || || 31 || 68451 || -

| 1984 || 68020 || || || 32 || 68851 || 68881

| - || 68EC020 || || || 24 || - || -

| 1987 || 68030 || (max ), || || 32 || MMU || 68881

| || 68EC030 || , || || 32 || - || 68881

| 1991 || 68040 || , || || 32 || MMU || FPU

| || 68LC040 || , || || 32 || MMU || FPU

| || 68LC060 || , ||