Motorola 68000

The Motorola 68000 (sometimes shortened to Motorola 68k or m68k and usually pronounced "sixty-eight-thousand") is a 16/32-bit complex instruction set computer (CISC) microprocessor, introduced in 1979 by Motorola Semiconductor Products Sector.

The design implements a 32-bit instruction set, with 32-bit registers and a 16-bit internal data bus. and has a 16-bit external data bus. For this reason, Motorola termed it a 16/32-bit processor.

As one of the first widely available processors with a 32-bit instruction set, large unsegmented address space, and relatively high speed for the era, the 68k was a popular design through the 1980s. It was widely used in a new generation of personal computers with graphical user interfaces, including the Macintosh 128K, Amiga, Atari ST, and X68000, as well as video game consoles such as the Sega Genesis/Mega Drive console. Several arcade game systems also used the 68000.

Later processors in the Motorola 68000 series, beginning with the Motorola 68020, use full 32-bit ALUs and have full 32-bit address and data buses, speeding up 32-bit operations and allowing 32-bit addressing, rather than the 24-bit addressing of the 68000 and 68010 or the 31-bit addressing of the Motorola 68012. The original 68k is generally software forward-compatible with the rest of the line despite being limited to a 16-bit wide external bus. functionally identical clones and reproductions of the 68000 are still actively made.

Development

thumb|Motorola MC68000 ([[leadless chip carrier (CLCC) package)]]

thumb|Motorola MC68000 ([[plastic leaded chip carrier (PLCC) package)]]

6800

Motorola's first widely produced microprocessor was the 6800, introduced in early 1974 and available in quantity late that year. The company set itself the goal of selling 25,000 units by September 1976, a goal they did meet. Although a capable design, it was eclipsed by more powerful designs, such as the Zilog Z80, and less expensive designs, such as the MOS Technology 6502. By late 1976 sales were stagnant and the division was saved by a project for General Motors engine control and other tasks.

Moving to 16-bit

By the time the 6800 was introduced, a small number of 16-bit designs had come to market. These were generally modeled on minicomputer platforms like the Data General Nova or PDP-11. Based on the semiconductor manufacturing processes of the era, these were often multi-chip solutions like the National Semiconductor IMP-16, or the single-chip PACE that had issues with speed.

With the sales prospects for the 6800 dimming, but still cash-flush from the engine control sales, in late 1976 Colin Crook, Operations Manager, began considering how to successfully win future sales. They were aware that Intel was working on a 16-bit extension of their 8080 series, which would emerge as the Intel 8086, and had heard rumors of a 16-bit Zilog Z80, which became the Z8000. These would use new design techniques that would eliminate the problems seen in earlier 16-bit systems.

Motorola knew that if they launched a product similar to the 8086, within 10% of its capabilities, Intel would outperform them in the market. In order to compete, they set themselves the goal of being two times as powerful at the same cost, or one-half the cost with the same performance. Crook decided that they would attack the high-end of the market with the most powerful processor on the market. Another 16-bit would not do, their design would have to be bigger, and that meant having some 32-bit features. Crook had decided on this approach by the end of 1976.

MACSS

Crook formed the Motorola Advanced Computer System on Silicon (MACSS) project to build the design and hired Tom Gunter to be its principal architect. Gunter began forming his team in January 1977. The performance goal was set at 1 million instructions per second (MIPS). They wanted the design to not only win back microcomputer vendors like Apple Computer and Tandy, but also minicomputer companies like NCR and AT&T.

The team decided to abandon an attempt at backward compatibility with the 6800, as they felt the 8-bit designs were too limited to be the basis for new designs. The new system was influenced by the PDP-11, the most popular minicomputer design of the era. At the time, a key concept in minis was the concept of an orthogonal instruction set, in which every operation was allowed to work on any sort of data, and the PDP-11 instruction set was considered the canonical example of this concept. This resulted in many different instructions, which were minor variations that changed where the data came from. To feed the correct data into the internal units, MACSS made extensive use of microcode, essentially small programs in read only memory that gathered up the required data, performed the operations, and then wrote out the results. This was common in mainframes and minis, but MACSS would be among the first to use this technique in a microprocessor.

There was a large amount of support hardware for the 6800 that would remain useful, things like UARTs and similar interfacing systems. For this reason, the new design retained a bus protocol compatibility mode for existing 6800 peripheral devices. Indeed, Gunter's own 1979 article introducing the 68000 highlighted it as a silicon-gate depletion-mode HMOS design. Whatever the degree of Motorola's process and manufacturing deficits in the early days, the team was undeterred and would not compromise in its pursuit of a microprocessor with industry-leading performance.

Sampling and production

Formally introduced in September 1979, initial samples were released in February 1980, with production chips available over the counter in November. Initial speed grades were 4, 6, and 8 MHz. 10 MHz chips became available during 1981, and 12.5 MHz chips by June 1982.

The KDM board came with socketed ROM chips that contained Motorola's new MacsBug debugger. A switch on the KDM board activated the debugger. MacsBug was later used in Apple's early Macintosh computers.

Apple adoption

By the start of 1981, the 68k was winning orders in the high end, and Gunter began to approach Apple to win their business. At that time, the 68k sold for about $125 in quantity. In meetings with Steve Jobs, Jobs talked about using the 68k in the Apple Lisa, but stated "the real future is in this product that I'm personally doing. If you want this business, you got to commit that you'll sell it for $15." Motorola countered by offering to sell it at $55 at first, then step down to $35, and so on. Jobs agreed, and the Macintosh moved from the 6809 to the 68k. The average price eventually reached $14.76. According to Apple, The First 50 Years, Jobs reportedly slid a clone chip being prepared by Hitachi to Motorola CEO Robert Galvin on a piece of sushi in order to negotiate.

Variants

In 1982, the 68000 received a minor update to its instruction set architecture (ISA) to support virtual memory and to conform to the Popek and Goldberg virtualization requirements. The updated chip is called the 68010. It also adds a new "loop mode" which speeds up small loops, and increases overall performance by about 10% at the same clock speeds. A further extended version, which exposes 31 bits of the address bus, was also produced in small quantities as the 68012.

To support lower-cost systems and control applications with smaller memory sizes, Motorola introduced the 8-bit compatible 68008, also in 1982. This is a 68000 with an 8-bit data bus and a smaller (20-bit) address bus. After 1982, Motorola devoted more attention to the 68020 and 88000 projects.

Second-sourcing

thumb|[[Hitachi HD68000]]

thumb|Thomson TS68000

Several other companies were second-source manufacturers of the HMOS 68000. These included Hitachi (HD68000), who shrank the feature size to 2.7 μm for their 12.5 MHz version,

CMOS versions

thumb|Motorola MC68HC000LC8

The 68HC000, the first CMOS version of the 68000, was designed by Hitachi and jointly introduced in 1985. Motorola offered it as the MC68HC000 while Hitachi offered it as the HD68HC000. The 68HC000 offers speeds of 8–20 MHz. Aside from using CMOS circuitry, it behaved identically to the HMOS 68000, but the change to CMOS greatly reduced its power consumption. The original HMOS 68000 consumed around 1.35 watts at an ambient temperature of 25 °C, regardless of clock speed, while the 68HC000 consumed only 0.13 watts at 8 MHz and 0.38 watts at 20 MHz. (Unlike CMOS circuits, HMOS still draws power when idle, so power consumption varies little with clock rate.) Apple selected the 68HC000 for use in the Macintosh Portable and PowerBook 100.

Motorola replaced the 68008 with the 68HC001 in 1990. It resembles the 68HC000 in most respects, but its data bus can operate in either 16-bit or 8-bit mode, depending on the value of an input pin at reset. Thus, like the 68008, it can be used in systems with cheaper 8-bit memories.

The later evolution of the 68000 focused on more modern embedded control applications and on-chip peripherals. The 68EC000 chip and SCM68000 core removed the M6800 peripheral bus, as well as excluding the MOVE from SR instruction from user mode programs, making the 68EC000 and 68SEC000 the only 68000 CPUs not 100% object code compatible with previous 68000 CPUs when run in User Mode. When run in Supervisor Mode, there is no difference. The latter method was done so that the 68EC000 and SCM68000 can meet Popek and Goldberg virtualization requirements, and was also later implemented into its successor, the 68010. In 1996, Motorola updated the standalone core with fully static circuitry, drawing only 2 μW in low-power mode; this became known as the 68SEC000.

Motorola ceased production of the HMOS 68000 as well as the 68008, 68010, 68330, and 68340 on June 1, 1996, but its spin-off company Freescale Semiconductor (merged with NXP) was still producing the 68HC000, 68HC001, 68EC000 and 68SEC000, as well as the 68302 and 68306 microcontrollers and later versions of the DragonBall family. The 68000's architectural descendants, the 680x0, CPU32, and Coldfire families, were also still in production. More recently, with the Sendai fab closure in 2010, all 68HC000, 68020, 68030 and 68882 parts have been discontinued, leaving only the 68SEC000 in production until it too was discontinued. leaving only the 68331 and 68332 as the remaining members of the 683xx family in production.

In 2024, Rochester Electronics was given a license by NXP to continue producing the 68HC000 alongside other members of the 68000 family; both the physical design and test programs were transferred from NXP to Rochester in order to continue providing an authorized source to the market. The 68HC000 processors provided by Rochester Electronics uses a clone of the J82M mask set manufactured by Tohoku Semiconductor Corporation (TSC) in Japan at the TSC6 wafer fab, which was the last mask set used by Motorola for the 68HC000 to replace the previous E72N and G73K mask sets manufactured in the United States.

As a microcontroller core

Since being succeeded by "true" 32-bit microprocessors, the 68000 is used as the core of many microcontrollers. In 1989, Motorola introduced the 68302 communications processor. This processor was formerly supplied by Freescale and NXP after Motorola spun off its semiconductor business in 2004. and the 68000 and its successors became the dominant CPUs for Unix-based workstations including Sun workstations and Apollo/Domain workstations.

In 1981, Motorola introduced the Motorola 68000 Educational Computer Board, a single-board computer for educational and training purposes which in addition to the 68000 itself contained memory, I/O devices, programmable timer and wire-wrap area for custom circuitry. The board remained in use in US colleges as a tool for learning assembly programming until the early 1990s.

At its introduction, the 68000 was first used in high-priced systems, including multiuser microcomputers like the WICAT 150, early Alpha Microsystems computers, Sage II / IV, Tandy 6000 / TRS-80 Model 16, and Fortune 32:16; single-user workstations such as Hewlett-Packard's HP 9000 Series 200 systems, the first Apollo/Domain systems, Sun Microsystems' Sun-1, and the Corvus Concept; and graphics terminals like Digital Equipment Corporation's VAXstation 100 and Silicon Graphics' IRIS 1000 and 1200. Unix systems rapidly moved to the more capable later generations of the 68k line, which remained popular in that market throughout the 1980s.

By the mid-1980s, falling production cost made the 68000 viable for use in personal computers starting with the Apple Lisa and Macintosh, and followed by the Amiga, Atari ST, and X68000.

The Sinclair QL microcomputer, along with its derivatives, such as the ICL One Per Desk business terminal, was the most commercially important utilisation of the 68008. Helix Systems (in Missouri, United States) designed an extension to the SWTPC SS-50 bus, the SS-64, and produced systems built around the 68008 processor. 68000 and 68008 second processors were released for the BBC Micro in 1984 and 1985 respectively, and according to Steve Furber contributed to Acorn developing the ARM.

While the adoption of RISC and x86 displaced the 68000 series as desktop/workstation CPU, the processor found substantial use in embedded applications. By the early 1990s, quantities of 68000 CPUs could be purchased for less than 30 USD per part.

The 68000 also saw great success as an embedded controller. As early as 1981, laser printers such as the Imagen Imprint-10 were controlled by external boards equipped with the 68000. The first HP LaserJet, introduced in 1984, came with a built-in 8 MHz 68000. Other printer manufacturers adopted the 68000, including Apple with its introduction of the LaserWriter in 1985, the first PostScript laser printer. The 68000 continued to be widely used in printers throughout the rest of the 1980s, persisting well into the 1990s in low-end printers.

The 68000 was successful in the field of industrial control systems. Among the systems benefited from having a 68000 or derivative as their microprocessor were families of programmable logic controllers (PLCs) manufactured by Allen-Bradley, Texas Instruments and subsequently, following the acquisition of that division of TI, by Siemens. Users of such systems do not accept product obsolescence at the same rate as domestic users, and it is entirely likely that despite having been installed over 20 years ago, many 68000-based controllers will continue in reliable service well into the 21st century.

In a number of digital oscilloscopes from the 80s, the 68000 has been used as a waveform display processor; some models including the LeCroy 9400/9400A also use the 68000 as a waveform math processor (including addition, subtraction, multiplication, and division of two waveforms/references/waveform memories), and some digital oscilloscopes using the 68000 (including the 9400/9400A) can also perform fast Fourier transform functions on a waveform.

The 683XX microcontrollers, based on the 68000 architecture, are used in networking and telecom equipment, television set-top boxes, laboratory and medical instruments, and even handheld calculators. The MC68302 and its derivatives have been used in many telecom products from Cisco, 3com, Ascend, Marconi, Cyclades and others. Past models of the Palm PDAs and the Handspring Visor used the DragonBall, a derivative of the 68000. AlphaSmart used the DragonBall family in later versions of its portable word processors. Texas Instruments used the 68000 in its high-end graphing calculators, the TI-89 and TI-92 series and Voyage 200.

A modified version of the 68000 formed the basis of the IBM XT/370 hardware emulator of the System 370 processor.

Video games

Several video game manufacturers have used the 68000 as the backbone of many arcade games, game consoles and some handhelds since its release.

Arcade games

thumb|250px|Two Hitachi 68HC000 CPUs being used on an arcade-game PCB

Atari's Food Fight, from 1983, was one of the first 68000-based arcade games. Others included arcade game platforms such as Sega's System 16, Capcom's CP System and CP System II, as well as SNK's Neo Geo of the early 1990s, which also had a home console version.

Certain arcade games (such as Steel Gunner and others based on Namco System 2 and various Sega arcade system boards in the Super Scalar series) use a dual 68000 CPU configuration, and systems with a triple 68000 CPU configuration also exist (such as Galaxy Force and others based on the Sega Y Board), along with a quad 68000 CPU configuration, which has been used by Jaleco (one 68000 for sound has a lower clock rate compared to the other 68000 CPUs) for games such as Big Run and Cisco Heat; another, fifth 68000 (at a different clock rate than the other 68000 CPUs) was used in the Jaleco arcade game Wild Pilot for input/output (I/O) processing.

Consoles and handhelds

thumb|The [[Sega Genesis|Genesis video game console uses a 68000 as its primary CPU.]]

In the late 1980s, the 68000 was inexpensive enough to power home game consoles. The first was Sega's Genesis console in 1988, where the 68000 was the primary CPU. It is also in the system's Sega CD add-on (which has three CPUs, two of them 68000s). The Neo Geo AES (1990), based on its arcade counterpart, has the 68000 as its main CPU. Other consoles with 68000's are the educational Pico (1993), the multi-processor Jaguar (1993), and the handheld Genesis Nomad (1995). The 1994 Saturn contains the 68EC000 (an embedded version of the 68000) as a sound coprocessor.

Architecture

{| class="infobox" style="font-size:88%;width:34em;"

|+ Motorola 68000 registers

{| style="font-size:88%;"

| style="width:10px; text-align:left" | 31

| style="width:40px; text-align:center"| ...

| style="width:10px; text-align:right" | 23

| style="width:40px; text-align:center"| ...

| style="width:10px; text-align:center"| 15

| style="width:40px; text-align:center"| ...

| style="width:10px; text-align:center"| 07

| style="width:40px; text-align:center"| ...

| style="width:10px; text-align:center"| 00

| style="width:auto; background:white; color:black" | (bit position)

|colspan="10" | Data registers

|- style="background:silver;color:black"

| style="text-align:center;" colspan="9"| D0

| style="background:white; color:black" | Data 0

|- style="background:silver;color:black"

| style="text-align:center;" colspan="9"| D1

| style="background:white; color:black" | Data 1

|- style="background:silver;color:black"

| style="text-align:center;" colspan="9"| D2

| style="background:white; color:black" | Data 2

|- style="background:silver;color:black"

| style="text-align:center;" colspan="9"| D3

| style="background:white; color:black" | Data 3

|- style="background:silver;color:black"

| style="text-align:center;" colspan="9"| D4

| style="background:white; color:black" | Data 4

|- style="background:silver;color:black"

| style="text-align:center;" colspan="9"| D5

| style="background:white; color:black" | Data 5

|- style="background:silver;color:black"

| style="text-align:center;" colspan="9"| D6

| style="background:white; color:black" | Data 6

|- style="background:silver;color:black"

| style="text-align:center;" colspan="9"| D7

| style="background:white; color:black" | Data 7

|colspan="10" | Address registers

|- style="background:silver;color:black"

| style="text-align:center" colspan="3" |  

| style="text-align:center;padding-right:18%" colspan="6"| A0

| style="background:white; color:black" | Address 0

|- style="background:silver;color:black"

| style="text-align:center" colspan="3" |  

| style="text-align:center;padding-right:18%" colspan="6"| A1

| style="background:white; color:black" | Address 1

|- style="background:silver;color:black"

| style="text-align:center" colspan="3" |  

| style="text-align:center;padding-right:18%" colspan="6"| A2

| style="background:white; color:black" | Address 2

|- style="background:silver;color:black"

| style="text-align:center" colspan="3" |  

| style="text-align:center;padding-right:18%" colspan="6"| A3

| style="background:white; color:black" | Address 3

|- style="background:silver;color:black"

| style="text-align:center" colspan="3" |  

| style="text-align:center;padding-right:18%" colspan="6"| A4

| style="background:white; color:black" | Address 4

|- style="background:silver;color:black"

| style="text-align:center" colspan="3" |  

| style="text-align:center;padding-right:18%" colspan="6"| A5

| style="background:white; color:black" | Address 5

|- style="background:silver;color:black"

| style="text-align:center" colspan="3" |  

| style="text-align:center;padding-right:18%" colspan="6"| A6

| style="background:white; color:black" | Address 6

|colspan="10" | Stack pointers

|- style="background:silver;color:black"

| style="text-align:center" colspan="3"|  

| style="text-align:center;padding-right:18%" colspan="6"| A7 / USP

| style="background:white; color:black;"| Stack Ptr (user)

|- style="background:silver;color:black"

| style="text-align:center" colspan="3"|  

| style="text-align:center;padding-right:18%" colspan="6"| A7' / SSP

| style="background:white; color:black;"| Stack Ptr (supervisor)

|colspan="10" | Program counter

|- style="background:silver;color:black"

| style="text-align:center" colspan="3"|  

| style="text-align:center;padding-right:18%" colspan="6"| PC

| style="background:white; color:black;"| Program Counter

{| style="font-size:88%;"

|colspan="17" | Condition Code Register

| style="width:10px; text-align:center"| 15

| style="width:10px; text-align:center"| 14

| style="width:10px; text-align:center"| 13

| style="width:10px; text-align:center"| 12

| style="width:10px; text-align:center"| 11

| style="width:10px; text-align:center"| 10

| style="width:10px; text-align:center"| 09

| style="width:10px; text-align:center"| 08

| style="width:10px; text-align:center"| 07

| style="width:10px; text-align:center"| 06

| style="width:10px; text-align:center"| 05

| style="width:10px; text-align:center"| 04

| style="width:10px; text-align:center"| 03

| style="width:10px; text-align:center"| 02

| style="width:10px; text-align:center"| 01

| style="width:10px; text-align:center"| 00

| style="width:auto; background:white; color:black" | (bit position)

|- style="background:silver;color:black"

| style="text-align:center" colspan="2"| T

| style="text-align:center"| S

| style="text-align:center"| M

| style="text-align:center"| 0

| style="text-align:center" colspan="3"| I

| style="text-align:center"| 0

| style="text-align:center"| X

| style="text-align:center"| N

| style="text-align:center"| Z

| style="text-align:center"| V

| style="text-align:center"| C

| style="background:white; color:black" | CCR

Address bus

The 68000 has a 24-bit external address bus and two byte-select signals "replaced" A0. These 24 lines can therefore address 16 MB of physical memory with byte resolution. Address storage and computation uses 32 bits internally; however, the 8 high-order address bits are ignored due to the physical lack of device pins. This allows it to run software written for a logically flat 32-bit address space, while accessing only a 24-bit physical address space.  Motorola's intent with the internal 32-bit address space was forward compatibility, making it feasible to write 68000 software that would take full advantage of later 32-bit implementations of the 68000 instruction set.

Instruction set

The designers attempted to make the assembly language orthogonal. That is, instructions are divided into operations and address modes, and almost all address modes are available for almost all instructions. There are 56 instructions and a minimum instruction size of 16 bits. Many instructions and addressing modes are longer to include more address or mode bits.

Privilege levels

The CPU, and later the whole family, implements two levels of privilege. User mode gives access to everything except privileged instructions such as interrupt level controls. Supervisor privilege gives access to everything. An interrupt always becomes supervisory. The supervisor bit is stored in the status register, and is visible to user programs. To create a function that took a fixed cycle count required the addition of extra code after the multiply instruction. This would typically consume extra cycles for each bit that wasn't set in the original multiplication operand.

Most instructions are dyadic, that is, the operation has a source, and a destination, and the destination is changed. Notable instructions are:

Arithmetic: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU (unsigned divide), DIVS (signed divide), NEG (additive negation), and CMP (comparison, done by subtracting the arguments and setting the status bits without storing the result)
Binary-coded decimal arithmetic: ABCD, NBCD, and SBCD
Logic: EOR (exclusive or), AND, NOT (logical not), OR (inclusive or)
Shifting: (logical, i.e. right shifts put zero in the most-significant bit) LSL, LSR, (arithmetic shifts, i.e. sign-extend the most-significant bit) ASR, ASL, (rotates through eXtend and not) ROXL, ROXR, ROL, ROR
Bit test and manipulation in memory or data register: BSET (set to 1), BCLR (clear to 0), BCHG (invert) and BTST (no change). All of these instructions first test the destination bit and set (clear) the CCR Z bit if the destination bit is 0 (1), respectively.
Multiprocessing control: TAS, test-and-set, performed an indivisible bus operation, permitting semaphores to be used to synchronize several processors sharing a single memory
Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to subroutine), RTS (return from subroutine), RTE (return from exception, i.e. an interrupt), TRAP (trigger a software exception similar to software interrupt), CHK (a conditional software exception)
Branch: Bcc (where the "cc" specified one of 14 tests of the condition codes in the status register: equal, greater than, less-than, carry, and most combinations and logical inversions, available from the status register). The remaining two possible conditions (always true and always false) have separate instruction mnemonics, BRA (branch always), and BSR (branch to subroutine).
Decrement-and-branch: DBcc (where "cc" was as for the branch instructions), which, provided the condition was false, decremented the low word of a D-register and, if the result was not -1 ($FFFF), branched to a destination. This use of −1 instead of 0 as the terminating value allowed the easy coding of loops that had to do nothing if the count was 0 to start with, with no need for another check before entering the loop. This also facilitated nesting of DBcc.

68EC000

thumb|Motorola 68EC000 controller

The 68EC000 is a low-cost version of the 68000 with a slightly different pinout, designed for embedded controller applications. The 68EC000 can have either a 8-bit or 16-bit data bus, switchable at reset. The processors also have some minor changes to conform to the Popek and Goldberg virtualization requirements, which includes the MOVE from SR instruction being privileged.

The processors are available in a variety of speeds including 8 and 16 MHz configurations, producing 2,100 and 4,376 Dhrystones each. These processors have no floating-point unit, and it is difficult to implement an FPU coprocessor (MC68881/2) with one because the EC series lacks necessary coprocessor instructions.

The 68EC000 was used as a controller in many audio applications, including Ensoniq musical instruments and sound cards, where it was part of the MIDI synthesizer. On Ensoniq sound boards, the controller provided several advantages compared to competitors without a CPU on board. The processor allowed the board to be configured to perform various audio tasks, such as MPU-401 MIDI synthesis or MT-32 emulation, without the use of a terminate-and-stay-resident program. This improved software compatibility, lowered CPU usage, and eliminated host system memory usage.

The Motorola 68EC000 core was later used in the m68k-based DragonBall processors from Motorola/Freescale.

It also was used as a sound controller in the Sega Saturn game console and as a controller for the HP JetDirect Ethernet controller boards for the mid-1990s HP LaserJet printers.

Example code

The 68000 assembly code below is for a subroutine named , which copies a null-terminated string of 8-bit characters to a destination string, converting all alphabetic characters to lower case.

00100000

00100000 4E56 0000

00100004 306E 0008

00100008 326E 000C

0010000C 1018

0010000E 0C40 0041

00100012 6500 000E

00100016 0C40 005A

0010001A 6200 0006

0010001E 0640 0020

00100022 12C0

00100024 66E6

00100026 4E5E

00100028 4E75

0010002A

</syntaxhighlight>

; strtolower:

; Copy a null-terminated ASCII string, converting

; all alphabetic characters to lower case.

;

; Entry parameters:

; (SP+0): Return address

; (SP+4): Source string address

; (SP+8): Target string address

org $00100000 ;Start at 00100000

strtolower public

link a6,#0 ;Set up stack frame

movea 8(a6),a0 ;A0 = src, from stack

movea 12(a6),a1 ;A1 = dst, from stack

loop move.b (a0)+,d0 ;Load D0 from (src), incr src

cmpi #'A',d0 ;If D0 < 'A',

blo copy ;skip

cmpi #'Z',d0 ;If D0 > 'Z',

bhi copy ;skip

addi #'a'-'A',d0 ;D0 = lowercase(D0)

copy move.b d0,(a1)+ ;Store D0 to (dst), incr dst

bne loop ;Repeat while D0 <> NUL

unlk a6 ;Restore stack frame

rts ;Return

end

</syntaxhighlight>

The subroutine establishes a call frame using register A6 as the frame pointer. This kind of calling convention supports reentrant and recursive code and is typically used by languages like C and C++. The subroutine then retrieves the parameters passed to it ( and ) from the stack. It then loops, reading an ASCII character (one byte) from the string, checking whether it is a capital alphabetic character, and if so, converting it into a lower-case character, otherwise leaving it as it is, then writing the character into the string. Finally, it checks whether the character was a null character; if not, it repeats the loop, otherwise it restores the previous stack frame (and A6 register) and returns. Note that the string pointers (registers A0 and A1) are auto-incremented in each iteration of the loop.

In contrast, the code below is for a stand-alone function, even on the most restrictive version of AMS for the TI-89 series of calculators, being kernel-independent, with no values looked up in tables, files or libraries when executing, no system calls, no exception processing, minimal registers to be used, nor the need to save any. It is valid for historical Julian dates from 1 March 1 AD, or for Gregorian ones. In less than two dozen operations it calculates a day number compatible with ISO 8601 when called with three inputs stored at their corresponding LOCATIONS:

;

; WDN, an address - for storing result d0

; FLAG, 0 or 2 - to choose between Julian or Gregorian, respectively

; DATE, year0mda - date stamp as binary word&byte&byte in basic ISO-format

;(YEAR, year ~ YEAR=DATE due to big-endianness)

;

; Apply step 1 - Lachman's congruence

;

; Apply step 2 - Finding spqr as the year of the Julian leap day preceding DATE

;

; (Apply step 0 - Gregorian adjustment)

;

; Days of the week correspond to day numbers of the week as:

; Sun=0 Mon=1 Tue=2 Wed=3 Thu=4 Fri=5 Sat=6

;

Notes

References

Bibliography

External links

comp.sys.m68k FAQ
Descriptions of assembler instructions
68000 images and descriptions at cpu-collection.de
EASy68K, an open-source 68k assembler for Windows
the 68k and m88k resource – with information on Motorola's VME based 68k boards

Motorola 68000

Development

6800

Moving to 16-bit

MACSS

Sampling and production

Apple adoption

Variants

Second-sourcing

CMOS versions

As a microcontroller core

Video games

Arcade games

Consoles and handhelds

Architecture

Address bus

Instruction set

Privilege levels

68EC000

Example code

Notes

See also

References

Bibliography

Further reading

External links