thumb|MII connector on a [[Sun Ultra series|Sun Ultra 1 Creator workstation]]
The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet (i.e., ) medium access control (MAC) block to a PHY chip. The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being media independent means that different types of PHY devices for connecting to different media (i.e. twisted pair, fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. Thus, any MAC may be used with any PHY, independent of the network signal transmission medium.
The MII can be used to connect a MAC to an external PHY using a pluggable connector or directly to a PHY chip on the same PCB. On older PCs, the CNR connector Type B carried MII signals.
Network data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC). The original MII transfers network data using 4-bit nibbles in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve throughput. The original MII design has been extended to support reduced signals and increased speeds. The aberration xMII stands for generic media-independent interface, which includes:
- Reduced media-independent interface (RMII)
- Gigabit media-independent interface (GMII)
- Reduced gigabit media-independent interface (RGMII)
- Serial media-independent interface (SMII)
- Serial gigabit media-independent interface (serial GMII, SGMII)
- High serial gigabit media-independent interface (HSGMII)
- Quad serial gigabit media-independent interface (QSGMII)
- Penta serial gigabit media-independent interface (PSGMII)
- 10-gigabit media-independent interface (XGMII)
The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.
Standard MII
The standard MII features a small set of registers:
Signal levels
TTL logic levels are used for or logic. Input high threshold is and low is . The specification states that inputs should be tolerant; however, some popular chips with RMII interfaces are not tolerant. Newer devices may support and logic.
The RMII signals are treated as lumped signals rather than transmission lines. However, the IEEE version of the related MII standard specifies trace impedance. National recommends running traces with series termination resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under long and matched within on length to minimize skew.
Transmitter signals
{| class="wikitable"
|-
! Signal name
! Description
|-
| GTXCLK
| Clock signal for gigabit TX signals (125 MHz)
|-
| TXCLK
| Clock signal for signals
|-
| TXD[7..0]
| Data to be transmitted
|-
| TXEN
| Transmitter enable
|-
| TXER
| Transmitter error (used to intentionally corrupt a packet, if necessary)
|}
There are two transmitter clocks. The clock used depends on whether the PHY is operating at gigabit or speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for or 2.5 MHz for connections. In contrast, the receiver uses a single clock signal recovered from the incoming data.
Receiver signals
{| class="wikitable"
|-
! Signal name
! Description
|-
| RXCLK
| Received clock signal (recovered from incoming received data)
|-
| RXD[7..0]
| Received data
|-
| RXDV
| Signifies data received is valid
|-
| RXER
| Signifies data received has errors
|-
| COL
| Collision detect (half-duplex connections only)
|-
| CS
| Carrier sense (half-duplex connections only)
|}
Management signals
{| class="wikitable"
|-
! Signal name
! Description
|-
| MDC
| Management interface clock
|-
| MDIO
| Management interface I/O bidirectional pin.
|}
The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the Extended Status register. The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on the rising edge and (TXEN xor TXER) on the falling edge. This is the case for both and .
The transmit clock signal is always provided by the MAC on the TXC line. The receive clock signal is always provided by the PHY on the RXC line. Source-synchronous clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay, obviating the need for the PCB designer to add delay; this is known as RGMII-ID.
{| class="wikitable"
|+ RGMII signals
! Signal name
! Description
! Direction
|-
| TXC
| Clock signal
| MAC to PHY
|-
| TD[3..0]
| Data to be transmitted
| MAC to PHY
|-
| TX_CTL
| Multiplexing of transmitter enable and transmitter error
| MAC to PHY
|-
| RXC
| Received clock signal (recovered from incoming received data)
| PHY to MAC
|-
| RD[3..0]
| Received data
| PHY to MAC
|-
| RX_CTL
| Multiplexing of data received is valid and receiver error
| PHY to MAC
|-
| MDC
| Management interface clock
| MAC to PHY
|-
| MDIO
| Management interface I/O
| Bidirectional
|}
RGMII version 1.3 uses 2.5V CMOS, whereas RGMII version 2 uses 1.5V HSTL.
Serial gigabit media-independent interface
The serial gigabit media-independent interface (SGMII) is a variant of MII used for Gigabit Ethernet but can also carry Ethernet.
It uses differential pairs at 625 MHz clock frequency, DDR for TX and RX data and TX and RX clocks. It differs from GMII by its low-power and low pin-count 8b/10b-coded SerDes. The transmit and receive paths each use one differential pair for data and another differential pair for the clock. The TX/RX clocks must be generated on device output, but are optional on device input (clock recovery may be used alternatively). Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz.
High serial gigabit media independent interface
The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to . Sometimes this interface is also called OCSGMII (overclocked SGMII).
Quad serial gigabit media-independent interface
The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a interface. QSGMII, like SGMII, uses low-voltage differential signaling (LVDS) for the TX and RX data, and a single LVDS clock signal. QSGMII uses significantly fewer signal lines than four separate SGMII connections.
QSGMII predates NBASE-T and is used to connect multi-port PHYs to MACs, for example, in network routers.
The PSGMII (penta serial gigabit media-independent interface) uses the same signal lines as QSGMII, but operates at , which supports five 1 gigabit/s ports through one MII.
10 gigabit media-independent interface
10 gigabit media-independent interface (XGMII) is a standard defined in IEEE 802.3 designed for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board (PCB). It is now typically used for on-chip connections. PCB connections are now mostly accomplished with XAUI. XGMII features two 32-bit datapaths (Rx & Tx) and two four-bit control flows (Rxc and Txc), operating at 156.25 MHz DDR (312.5 MT/s).
See also
- Attachment Unit Interface (AUI)
- G.hn, an ITU-T recommendation that uses the term MII to refer to the interface between the data link layer and the physical layer.
- Gigabit interface converter (GBIC)
- List of interface bit rates
- Medium-dependent interface (MDI)
- Small form-factor pluggable (SFP) transceiver
- XFP transceiver
References
External links
- Texas Instruments AN-1405 DP83848 RMII
- Texas Instruments DP83848C PHY Data Sheet
- hp.com RGMIIv2_0_final_hp.pdf RGMII 2002-04-01 Version 2.0
- Altera 10 Gb Ethernet IP with XGMII and XAUI interfaces
- GMII Timing and Electrical Specification