MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.

There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.

The MIPS architecture has several optional extensions: MIPS-3D, a simple set of floating-point SIMD instructions dedicated to 3D computer graphics; MDMX (MaDMaX), a more extensive integer SIMD instruction set using 64-bit floating-point registers; MIPS16e, which adds compression to the instruction stream to reduce the memory programs require; and MIPS MT, which adds multithreading capability.

Computer architecture courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as Alpha. In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to RISC-V.

History

The first version of the MIPS architecture was designed by MIPS Computer Systems for its R2000 microprocessor, the first MIPS implementation. Both MIPS and the R2000 were introduced together in 1985. When MIPS II was introduced, MIPS was renamed MIPS I to distinguish it from the new version. In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from Silicon Graphics. MIPS V was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications. MIPS V implementations were never introduced. On May 12, 1997, Silicon Graphics announced the H1 ("Beast") and H2 ("Capitan") microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in the first half of 1999. The H1 and H2 projects were later combined and eventually canceled in 1998. While there have not been any MIPS V implementations, MIPS64 Release 1 (1999) was based on MIPS V and retains all of its features as an optional Coprocessor 1 (FPU) feature called Paired-Single.

When MIPS Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market. Through MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem, and the architecture definition was changed to define a 32-bit and a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999. MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V. According to the Product Marketing Director at MIPS, Release 4 was skipped because the number four is perceived as unlucky in many Asian cultures.

In December 2018, Wave Computing, the new owner of the MIPS architecture, announced that MIPS ISA would be open-sourced in a program dubbed the MIPS Open initiative. The program was intended to open up access to the most recent versions of both the 32-bit and 64-bit designs making them available without any licensing or royalty fees as well as granting participants licenses to existing MIPS patents.

In March 2019, MIPS Revision 6 was made available under a royalty-free license, but later that year the program was shut down again.

In March 2021, Wave Computing announced that the development of the MIPS architecture has ceased. The company has joined the RISC-V foundation and future processor designs will be based on the RISC-V architecture. In spite of this, some licensees such as Loongson are continuing with new extensions of MIPS-compatible ISAs on their own.

In January 2024, Loongson won a case over rights to use MIPS architecture.

Design

MIPS is a modular architecture supporting up to four coprocessors (COP0/1/2/3). In MIPS terminology, COP0 is the System Control Coprocessor (an essential part of the processor that is implementation-defined in MIPS I–V), COP1 is an optional floating-point unit (FPU), and COP2 and COP3 are optional implementation-defined coprocessors (MIPS III removed COP3 and reused its opcodes for other purposes). For example, in the PlayStation video game console, COP2 is the Geometry Transformation Engine (GTE), which accelerates the processing of geometry in 3D computer graphics.

Versions

MIPS I

MIPS is a load/store architecture (also known as a register-register architecture); except for the load/store instructions used to access memory, all instructions operate on the registers.

MIPS I has thirty-two 32-bit general-purpose registers (GPR). Register is hardwired to zero and writes to it are discarded. Register is the link register. For integer multiplication and division instructions, which run asynchronously from other instructions, a pair of 32-bit registers, HI and LO, are provided. There is a small set of instructions for copying data between the general-purpose registers and the HI/LO registers. The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries.

Instructions are divided into three types: R (register), I (immediate), and J (jump). Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target. A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given branch-likely versions that executed the instruction in the branch delay slot only if the branch is taken. MIPS IV was designed to mainly improve floating-point (FP) performance. To improve access to operands, an indexed addressing mode (base + index, both sourced from GPRs) for FP loads and stores was added, as were prefetch instructions for performing memory prefetching and specifying cache hints (these supported both the base + offset and base + index addressing modes).

MIPS IV added several features to improve instruction-level parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status register, bringing the total to eight. FP comparison and branch instructions were redefined so they could specify which condition bit was written or read (respectively); and the delay slot in between an FP branch that read the condition bit written to by a prior FP comparison was removed. Support for partial predication was added in the form of conditional move instructions for both GPRs and FPRs; and an implementation could choose between having precise or imprecise exceptions for IEEE 754 traps.

MIPS IV added several new FP arithmetic instructions for both single- and double-precision FPNs: fused-multiply add or subtract, reciprocal, and reciprocal square-root. The FP fused-multiply add or subtract instructions perform either one or two roundings (it is implementation-defined), to exceed or meet IEEE 754 accuracy requirements (respectively). The FP reciprocal and reciprocal square-root instructions do not comply with IEEE 754 accuracy requirements, and produce results that differ from the required accuracy by one or two units of last place (it is implementation defined). These instructions serve applications where instruction latency is more important than accuracy.

MIPS V

MIPS V added a new data type, the Paired Single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data.

MIPS32/MIPS64 Release 6 in 2014 added the following:

  • a new family of branches with no delay slot:
  • unconditional branches (BC) and branch-and-link (BALC) with a 26-bit offset,
  • conditional branch on zero/non-zero with a 21-bit offset,
  • full set of signed and unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC),
  • full set of branch-and-link which compare a register against zero (e.g. BGTZALC).
  • index jump instructions with no delay slot designed to support large absolute addresses.
  • instructions to load 16-bit immediates at bit position 16, 32 or 48, allowing to easily generate large constants.
  • PC-relative load instructions, as well as address generation with large (PC-relative) offsets.
  • bit-reversal and byte-alignment instructions (previously only available with the DSP extension).
  • multiply and divide instructions redefined so that they use a single register for their result).
  • instructions generating truth values now generate all zeroes or all ones instead of just clearing/setting the 0-bit,
  • instructions using a truth value now only interpret all-zeroes as false instead of just looking at the 0-bit.

Removed infrequently used instructions:

  • some conditional moves
  • branch likely instructions (deprecated in previous releases).
  • integer overflow trapping instructions with 16-bit immediate
  • integer accumulator instructions (together HI/LO registers, moved to the DSP Application-Specific Extension)
  • unaligned load instructions (LWL and LWR), (requiring that most ordinary loads and stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))

Reorganized the instruction encoding, freeing space for future expansions.

microMIPS

The microMIPS32/64 architectures are supersets of the MIPS32 and MIPS64 architectures (respectively) designed to replace the MIPS16e application-specific extension (ASE). A disadvantage of MIPS16e is that it requires a mode switch before any of its 16-bit instructions can be processed. microMIPS adds versions of the most-frequently used 32-bit instructions that are encoded as 16-bit instructions. This allows programs to intermix 16- and 32-bit instructions without having to switch modes. microMIPS was introduced alongside of MIPS32/64 Release 3, and each subsequent release of MIPS32/64 has a corresponding microMIPS32/64 version. A processor may implement microMIPS32/64 or both microMIPS32/64 and its corresponding MIPS32/64 subset. Starting with MIPS32/64 Release 6, support for MIPS16e ended, and microMIPS is the only form of code compression in MIPS.

Application-specific extensions

The base MIPS32 and MIPS64 architectures can be supplemented with a number of optional architectural extensions, which are collectively referred to as application-specific extensions (ASEs). These ASEs provide features that improve the efficiency and performance of certain workloads, such as digital signal processing.

MIPS MCU

Enhancements for microcontroller applications. The MCU ASE (application-specific extension) has been developed to extend the interrupt controller support, reduce the interrupt latency and enhance the I/O peripheral control function typically required in microcontroller system designs.

  • Separate priority and vector generation
  • Supports up to 256 interrupts in EIC (External Interrupt Controller) mode and eight hardware interrupt pins
  • Provides 16-bit vector offset address
  • Pre-fetching of the interrupt exception vector
  • Automated Interrupt Prologue – adds hardware to save and update system status before the interrupt handling routine
  • Automated Interrupt Epilogue – restores the system state previously stored in the stack for returning from the interrupt.
  • Interrupt Chaining – supports the service of pending interrupts without the need to exit the initial interrupt routine, saving the cycles required to store and restore multiple active interrupts
  • Supports speculative pre-fetching of the interrupt vector address. Reduces the number of interrupt service cycles by overlapping memory accesses with pipeline flushes and exception prioritization
  • Includes atomic bit set/clear instructions which enables bits within an I/O register that are normally used to monitor or control external peripheral functions to be modified without interruption, ensuring the action is performed securely.

MIPS16

MIPS16 is an Application-Specific Extension for MIPS I through to V designed by LSI Logic and MIPS Technologies, announced on October 21, 1996, alongside its first implementation, the LSI Logic TinyRISC processor. MIPS16 was subsequently licensed by NEC Electronics, Philips Semiconductors, and Toshiba (among others); and implemented as an extension to the MIPS I, II, an III architectures. MIPS16 decreases the size of application by up to 40% by using 16-bit instructions instead of 32-bit instructions and also improves power efficiency, the instruction cache hit rate, and is equivalent in performance to its base architecture. It is supported by hardware and software development tools from MIPS Technologies and other providers. MIPS16e is an improved version of MIPS16 first supported by MIPS32 and MIPS64 Release 1. MIPS16e2 is an improved version of MIPS16 that is supported by MIPS32 and MIPS64 (up to Release 5). Release 6 replaced it with microMIPS.

MIPS Digital Signal Processing (DSP)

The DSP ASE is an optional extension to the MIPS32/MIPS64 Release 2 and newer instruction sets which can be used to accelerate a large range of "media" computations—particularly audio and video. The DSP module comprises a set of instructions and state in the integer pipeline and requires minimal additional logic to implement in MIPS processor cores. Revision 2 of the ASE was introduced in the second half of 2006. This revision adds extra instructions to the original ASE, but is otherwise backwards-compatible with it. Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for a particular relevance to some key algorithm. Its main novel features (vs original MIPS32):

  • Saturating arithmetic (when a calculation overflows, deliver the representable number closest to the non-overflowed answer).
  • Fixed-point arithmetic on signed 32- and 16-bit fixed-point fractions with a range of -1 to +1 (these are widely called "Q31" and "Q15").
  • The existing integer multiplication and multiply-accumulate instructions, which deliver results into a double-size accumulator (called "hi/lo" and 64 bits on MIPS32 CPUs). The DSP ASE adds three more accumulators, and some different flavours of multiply-accumulate.
  • SIMD instructions operating on 4 x unsigned bytes or 2 x 16-bit values packed into a 32-bit register (the 64-bit variant of the DSP ASE supports larger vectors, too).
  • SIMD operations are basic arithmetic, shifts and some multiply-accumulate type operations.

MIPS SIMD architecture (MSA)

Instruction set extensions designed to accelerate multimedia.

  • Predefined scalable extensions for chips with more gates/transistors
  • 32 vector registers of 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, and 2 x 64 bit vector elements, all 128-bit in width
  • Includes operations for:
  • Efficient vector arithmetic on integer, fixed-point and floating-point data with full rounding and saturation options
  • Creating absolute values in vectors
  • Full precision multiplication and fused multiply-add
  • Conversions between integer, floating-point and fixed-point data
  • Vector-level comparison and branching without condition flags
  • Vector (1D) and array (2D) shuffling
  • Typed loads and stores for endian-independent operation
  • IEEE 754-2008 compliant
  • Element-precise floating-point exception signaling
  • Accelerates compute-intensive applications by leveraging generic compiler support
  • Created as a software-programmable solution for consumer electronics applications or functions not covered by dedicated hardware
  • Created for emerging data mining, feature extraction, multimedia processing, GUIs and high-performance scientific computing

MIPS virtualization

MIPS Revision 6 added native virtualization supported by hardware.

MIPS multi-threading

Each multi-threaded MIPS core can support up to two VPEs (Virtual Processing Elements) which share a single pipeline as well as other hardware resources. However, since each VPE includes a complete copy of the processor state as seen by the software system, each VPE appears as a complete standalone processor to an SMP Linux operating system. For more fine-grained thread processing applications, each VPE is capable of supporting up to nine TCs allocated across two VPEs. The TCs share a common execution unit but each has its own program counter and core register files so that each can handle a thread from the software. The MIPS MT architecture also allows the allocation of processor cycles to threads, and sets the relative thread priorities with an optional Quality of Service (QoS) manager block. This enables two prioritization mechanisms that determine the flow of information across the bus. The first mechanism allows the user to prioritize one thread over another. The second mechanism is used to allocate a specified ratio of the cycles to specific threads over time. The combined use of both mechanisms allows effective allocation of bandwidth to the set of threads, and better control of latencies. In real-time systems, system-level determinism is very critical, and the QoS block facilitates improvement of the predictability of a system. Hardware designers of advanced systems may replace the standard QoS block provided by MIPS Technologies with one that is specifically tuned for their application.

SmartMIPS

SmartMIPS is an Application-Specific Extension (ASE) designed by Gemplus International and MIPS Technologies to improve performance and reduce memory consumption for smart card software. It is supported by MIPS32 only, since smart cards do not require the capabilities of MIPS64 processors. Few smart cards use SmartMIPS.

MIPS Digital Media eXtension (MDMX)

Multimedia application accelerations that were common in the 1990s on RISC and CISC systems.

MIPS-3D

MIPS-3D is an extension to MIPS V that added 13 new instructions for improving the performance of 3D graphics applications. The instructions improved performance by reducing the number of instructions required to implement four common 3D graphics operations: vertex transformation, clipping, transformation and lighting.

For vertex transformation:

  • ADDR

For clipping:

  • CABS
  • BC1ANY2F
  • BC1ANY2T
  • BC1ANY4F
  • BC1ANY4T

For perspective division and normalization:

  • RECIP1
  • RECIP2
  • RSQRT1
  • RSQRT2

Calling conventions

MIPS has had several calling conventions, especially on the 32-bit platform.

The O32 ABI is the most commonly used ABI, owing to its status as the original System V ABI for MIPS. It is strictly stack-based, with only four registers (-) available to pass arguments. Space on the stack is reserved in case the callee needs to save its arguments, but the registers are not stored there by the caller. The return value is stored in register ; a second return value may be stored in . The ABI took shape in 1990 and was last updated in 1994. This perceived slowness, along with an antiquated floating-point model with only 16 registers, has encouraged the proliferation of many other calling conventions. It is only defined for 32-bit MIPS, but GCC has created a 64-bit variation called O64.

For 64-bit, the N64 ABI by Silicon Graphics is most commonly used. The most important improvement is that eight registers are now available for argument passing; it also increases the number of floating-point registers to 32. There is also an ILP32 version called N32, which uses 32-bit pointers for smaller code, analogous to the x32 ABI. Both run under the 64-bit mode of the CPU. EABI inspired MIPS Technologies to propose a more radical "NUBI" ABI additionally reuse argument registers for the return value. MIPS EABI is supported by GCC but not LLVM, and neither supports NUBI.

For all of O32 and N32/N64, the return address is stored in (). This is automatically set with the use of the JAL (jump and link) or JALR (jump and link register) instructions. The function prologue of a (non-leaf) MIPS subroutine pushes the return address (in ) to the stack.

On both O32 and N32/N64, the stack grows downwards, but the N32/N64 ABIs require 64-bit alignment for all stack entries. The frame pointer () is optional and in practice rarely used except when the stack allocation in a function is determined at runtime, for example, by calling <code>alloca()</code>.

For N32 and N64, the return address is typically stored 8 bytes before the stack pointer, although this may be optional.

For the N32 and N64 ABIs, a function must preserve the - registers, the global pointer ( or ), the stack pointer ( or ) and the frame pointer ( or ). The O32 ABI is the same except the calling function is required to save the register instead of the called function.

For multi-threaded code, the thread local storage pointer is typically stored in special hardware register and is accessed by using the mfhw (move from hardware) instruction. At least one vendor is known to store this information in the register which is normally reserved for kernel use, but this is not standard.

The and registers (, ) are reserved for kernel use and should not be used by applications since these registers can be changed at any time by the kernel due to interrupts, context switches or other events.

{| class="wikitable"

|+ Registers for O32 calling convention

! Name || Number || Use || Callee must preserve?

|-

!

| || constant 0 ||

|-

!

| || assembler temporary ||

|-

! –

| – || values for function returns and expression evaluation ||

|-

! –

| – || function arguments ||

|-

! –

| – || temporaries ||

|-

! –

| – || saved temporaries ||

|-

! –

| – || temporaries ||

|-

! –

| – || reserved for OS kernel ||

|-

!

| || global pointer || (except PIC code)

|-

!

| || stack pointer ||

|-

!

| || frame pointer ||

|-

!

| || return address ||

|}

{| class="wikitable"

|+ Registers for N32 and N64 calling conventions

! Name || Number || Use || Callee must preserve?

|-

!

| || constant 0 ||

|-

!

| || assembler temporary ||

|-

! –

| – || values for function returns and expression evaluation ||

|-

! –

| – || function arguments ||

|-

! –

| – || temporaries ||

|-

! –

| – || saved temporaries ||

|-

! –

| – || temporaries ||

|-

! –

| – || reserved for OS kernel ||

|-

!

| || global pointer ||

|-

!

| || stack pointer ||

|-

!

| || frame pointer ||

|-

!

| || return address ||

|}

Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. For example, -registers must be saved to the stack by a procedure that needs to use them, and and are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast, is changed automatically by any normal function call (ones that use ), and -registers must be saved by the program before any procedure call (if the program needs the values inside them after the call).

The userspace calling convention of position-independent code on Linux additionally requires that when a function is called the register must contain the address of that function. This convention dates back to the System V ABI supplement for MIPS.

Uses

MIPS processors are used in embedded systems such as residential gateways and routers. Originally, MIPS was designed for general-purpose computing. During the 1980s and 1990s, MIPS processors for personal, workstation, and server computers were used by many companies such as Digital Equipment Corporation, MIPS Computer Systems, NEC, Pyramid Technology, SiCortex, Siemens Nixdorf, Silicon Graphics, and Tandem Computers.

Historically, video game consoles such as the Nintendo 64, Sony PlayStation, PlayStation 2, and PlayStation Portable used MIPS processors. MIPS processors also used to be popular in supercomputers during the 1990s, but all such systems have dropped off the TOP500 list. These uses were complemented by embedded applications at first, but during the 1990s, MIPS became a major presence in the embedded processor market, and by the 2000s, most MIPS processors were for these applications.

In the mid- to late-1990s, it was estimated that one in three RISC microprocessors produced was a MIPS processor.

By the late 2010s, MIPS machines were still commonly used in embedded markets, including automotive, wireless router, LTE modems (mainly via MediaTek), and microcontrollers (for example the Microchip Technology PIC32M). They have mostly faded out of the personal, server, and application space.

Simulators

Open Virtual Platforms (OVP) includes the freely available for non-commercial use simulator OVPsim, a library of models of processors, peripherals and platforms, and APIs which enable users to develop their own models. The models in the library are open source, written in C, and include the MIPS 4K, 24K, 34K, 74K, 1004K, 1074K, M14K, microAptiv, interAptiv, proAptiv 32-bit cores and the MIPS 64-bit 5K range of cores. These models are created and maintained by Imperas and in partnership with MIPS Technologies have been tested and assigned the MIPS-Verified mark. Sample MIPS-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images. These platforms–emulators are available as source or binaries and are fast, free for non-commercial usage, and are easy to use. OVPsim is developed and maintained by Imperas and is very fast (hundreds of million of instructions per second), and built to handle multicore homogeneous and heterogeneous architectures and systems.

SPIM is a freely available MIPS32 simulator for use in education. Its newest version is called QtSpim and uses the Qt UI framework.

EduMIPS64 is a GPL graphical cross-platform MIPS64 CPU simulator written in Java/Swing, it started as a port of WinMIPS64, another MIPS64 simulator, and supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run.

MARS is another GUI-based MIPS emulator designed for use in education, specifically for use with Hennessy's Computer Organization and Design. It is no longer maintained.

Saturn is a GUI-based MIPS IDE with an assembler called Titan. It started as a project by a student at the University of Toronto as a replacement for MARS, which is no longer maintained. Saturn is now used in courses at the University of Toronto, and is maintained by students and faculty.

WebMIPS is a browser-based MIPS simulator with visual representation of a generic, pipelined processor. This simulator is quite useful for register tracking during step by step execution.

QtMips provides a simple 5-stage pipeline visualization as well as cache principle visualization for basic computer architectures courses. It is available both as a web application and as a downloadable program for Windows, Linux, and macOS.

More advanced free emulators are available from the GXemul (formerly known as the mips64emul project) and QEMU projects. They emulate the various MIPS III and IV microprocessors in addition to entire computer systems which use them.

Commercial simulators are available especially for the embedded use of MIPS processors, for example Wind River Simics (MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000, Broadcom/Netlogic ec4400, Cavium Octeon I), Imperas (all MIPS32 and MIPS64 cores), VaST Systems (R3000, R4000), and CoWare (the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K).

The CREATOR simulator is portable and allows the user to learn various assembly languages of different processors. Creator has examples with an implementation of MIPS32 and RISC-V instructions.

WepSIM is a browser-based simulator where a subset of MIPS instructions are micro-programmed.

This simulator is very useful in order to learn how a CPU works

at microprogramming level,

at MIPS assembly level,

with interruptions, etc.)

See also

  • DLX
  • List of MIPS architecture processors
  • MIPS architecture processors
  • Pipeline (computing)
  • Prpl Foundation

References

Further reading

  • MIPS Processors
  • Online MIPS emulator
  • MIPS Instructions - MIPS Instruction Set