Intel 8008 - WikiHQ

The Intel 8008 ("eight-thousand-eight" or "eighty-oh-eight") is an early 8-bit microprocessor capable of addressing 16 KB of memory, introduced in April 1972. The 8008 architecture was designed by Computer Terminal Corporation (CTC) and was implemented and manufactured by Intel. While the 8008 was originally designed for use in CTC's Datapoint 2200 programmable terminal, an agreement between CTC and Intel permitted Intel to market the chip to other customers after Seiko expressed an interest in using it for a calculator.

History

thumb|Intel 8008 wafer and two processors closed and open

In order to address several issues with the Datapoint 3300, including excessive heat radiation, Computer Terminal Corporation (CTC) designed the architecture of the 3300's planned successor with a CPU as part of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, CTC co-founder Austin O. "Gus" Roche turned to Intel, then primarily a vendor of memory chips. Roche met with Bob Noyce, who expressed concern with the concept; John Frassanito recalls that:

TI was able to make samples of the 1201 based on Intel drawings, calling it the TMX 1795. These proved to be buggy and were rejected. Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal using serial discrete TTL instead of waiting for a single-chip CPU. The new system was released as the Datapoint 2200 in the spring of 1970, with their first sale to General Mills on 25 May 1970. The 8008 went on to be a commercially successful design. This was followed by the popular Intel 8080, and then the hugely successful Intel x86 family. The operating system was burnt into a PROM. It was interrupt-driven, queued, and based on a fixed page size for programs and data.

The 8008 was the CPU for the very first commercial non-calculator personal computers (excluding the Datapoint 2200 itself): the US SCELBI kit and the pre-built French Micral N and Canadian MCM/70. It was also the controlling microprocessor for the first several models in Hewlett-Packard's 2640 family of computer terminals.

In 1973, Intel offered an instruction set simulator for the 8008 named INTERP/8. It was written in FORTRAN IV by Gary Kildall while he worked as a consultant for Intel.

Features

The 8008 architecture includes the following features:

48 instructions;
one 8-bit accumulator (A);
six 8-bit registers (B, C, D, E, H, L)
memory access of 16 KB using the H and L registers (HL) as a 14-bit address (the upper two bits are ignored);
8 bits for each memory cell;
interrupt capability;
a 14-bit program counter;
a seven-level, 14-bit call stack;
four condition code bits: carry (C), even parity (P), zero (Z), and sign (S).

The 8008 was provided in an 18-pin dual in-line package.

The 8008 was implemented in 10 μm silicon-gate enhancement-mode PMOS logic. Initial versions could work at clock frequencies up to 0.5 MHz. This was later increased in the 8008-1 to a specified maximum of 0.8 MHz. Instructions take between 3 and 11 T-states, where each T-state is 2 clock cycles.

Register–register loads and ALU operations take 5T (20 μs at 0.5 MHz), register–memory 8T (32 μs), while calls and jumps (when taken) take 11 T-states (44 μs).

The 8008 is a little slower in terms of instructions per second (36,000 to 80,000 at 0.8 MHz) than the 4-bit Intel 4004 and Intel 4040. but since the 8008 processes data 8 bits at a time and can access significantly more RAM, in most applications it has a significant speed advantage over these processors. The 8008 has 3,500 transistors.

The chip, limited by its 18-pin DIP, has a single 8-bit bus working triple duty to transfer 8 data bits, 14 address bits, and two status bits. The small package requires about 30 TTL support chips to interface to memory. For example, the 14-bit address, which can access "16 K × 8 bits of memory", needs to be latched by some of this logic into an external memory address register (MAR). The 8008 can access 8 input ports and 24 output ports.

The Intel 8085 is an electrically modernized version of the 8080 that uses depletion-mode transistors and also added two new instructions.

The Intel 8086, the original x86 processor, is a non-strict extension of the 8080, so it loosely resembles the original Datapoint 2200 design as well. Almost every Datapoint 2200 and 8008 instruction has an equivalent not only in the instruction set of the 8080, 8085, and Z80, but also in the instruction set of modern x86 processors (although the instruction encodings are different).

Instruction set

Instructions are one to three bytes long. The instruction format is an opcode byte, followed by up to two bytes of operands. Operands can be an address, a constant, a register, or the memory pointed to by the HL register pair, referenced as M. The 8008 has the JMP (jump) instruction that replaces the program counter with a new memory address. Additionally, the CAL (call) and RET (return) instructions provide seven levels of subroutine invocations. The RST (restart) instruction is a one byte shortcut to execute eight subroutines located in the first 64 instruction bytes. The subroutines are located at fixed addresses of 00h, 08h, 10h, ..., 38h. These are intended to be supplied to external hardware in order to invoke interrupt service routines, or they can be employed as fast calls. Direct copying may be made between any two registers or a register and memory. Eight math/logic functions are supported between the accumulator (A) and any register, memory, or immediate value. Results are always deposited to register A. Instructions operate on 8-bits only; there are no 16-bit operations. Increments and decrements are supported for most registers but, curiously, not A. Register A supports four rotate instructions.

All instructions execute in 3 to 11 states. Each state requires two clocks.

{|class="wikitable mw-collapsible" style="text-align:center"

!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| States ||rowspan=2| Description

! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3

| 0 || 0 || 0 || 0 || 0 || 0 || 0 || X || — || — ||align=left| || 4 ||align=left| Halt

| 0 || 0 ||colspan=3|DDD || 0 || 0 || 0 || — || — ||align=left| || 5 ||align=left| DDD ← DDD + 1 (except A and M)

| 0 || 0 ||colspan=3|DDD || 0 || 0 || 1 || — || — ||align=left| || 5 ||align=left| DDD ← DDD - 1 (except A and M)

| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || — || — ||align=left| || 5 ||align=left| A1-7 ← A0-6; A0 ← Cy ← A7

| 0 || 0 ||colspan=3|CC || 0 || 1 || 1 || — || — ||align=left| || 3/5 ||align=left| If cc true, P ← (stack)

| 0 || 0 ||colspan=3|ALU || 1 || 0 || 0 || data || — ||align=left| || 8 ||align=left| A ← A [ALU operation] data

| 0 || 0 ||colspan=3|N || 1 || 0 || 1 || — || — ||align=left| || 5 ||align=left| (stack) ← P, P ← N x 8

| 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || data || — ||align=left| || 8/9 ||align=left| DDD ← data

| 0 || 0 || X || X || X || 1 || 1 || 1 || — || — ||align=left| || 5 ||align=left| P ← (stack)

| 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || — || — ||align=left| || 5 ||align=left| A0-6 ← A1-7; A7 ← Cy ← A0

| 0 || 0 || 0 || 1 || 0 || 0 || 1 || 0 || — || — ||align=left| || 5 ||align=left| A1-7 ← A0-6; Cy ← A7; A0 ← Cy

| 0 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || — || — ||align=left| || 5 ||align=left| A0-6 ← A1-7; Cy ← A0; A7 ← Cy

| 0 || 1 ||colspan=3|CC || 0 || 0 || 0 || addlo || addhi ||align=left| || 9/11 ||align=left| If cc true, P ← add

| 0 || 1 || 0 || 0 ||colspan=3|port || 1 || — || — ||align=left| || 8 ||align=left| A ← Port(0-7)

| 0 || 1 ||colspan=5|port || 1 || — || — ||align=left| || 6 ||align=left| Port(8-31) ← A

| 0 || 1 ||colspan=3|CC || 0 || 1 || 0 || addlo || addhi ||align=left| || 9/11 ||align=left| If cc true, (stack) ← P, P ← add

| 0 || 1 || X || X || X || 1 || 0 || 0 || addlo || addhi ||align=left| || 11 ||align=left| P ← add

| 0 || 1 || X || X || X || 1 || 1 || 0 || addlo || addhi ||align=left| || 11 ||align=left| (stack) ← P, P ← add

| 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || — || — ||align=left| || 5/8 ||align=left| A ← A [ALU operation] SSS

| 1 || 1 ||colspan=3|DDD ||colspan=3|SSS || — || — ||align=left| ||5/7/8 ||align=left| DDD ← SSS

| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 || — || — ||align=left| || 4 ||align=left| Halt

! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || States || Description

!colspan=13|

!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU

|colspan=5| A || 0 || 0 || 0 ||colspan=2|FC, C false ||align=left|

|colspan=5| B || 0 || 0 || 1||colspan=2|FZ, Z false||align=left|

|colspan=5| C || 0 || 1 || 0||colspan=2|FS, S false ||align=left|

|colspan=5| D || 0 || 1 || 1||colspan=2|FP, P odd ||align=left|

|colspan=5| E || 1 || 0 || 0||colspan=2|TC, C true ||align=left|

|colspan=5| H || 1 || 0 || 1||colspan=2|TZ, Z true ||align=left|

|colspan=5| L || 1 || 1 || 0||colspan=2|TS, S true ||align=left|

|colspan=5| M || 1 || 1 || 1||colspan=2|TP, P even ||align=left|

!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU

Code example 1

The following 8008 assembly source code is for a subroutine named <code>MEMCPY</code> that copies a block of data bytes of a given size from one location to another. Intel's 8008 assembler supported only + and - operators. This example borrows the 8080's assembler AND and SHR (shift right) operators to select the low and high bytes of a 14-bit address for placement into the 8 bit registers. A contemporaneous 8008 programmer was expected to calculate the numbers and type them in for the assembler.

<pre>

001700 000

001701 000

001702 000

001703 000

001704 000

001705 000

002000 066 304

002002 056 003

002004 327

002005 060

002006 317

002007 302

002010 261

002011 053

002012 302

002013 024 001

002015 320

002016 301

002017 034 000

002021 310

002022 066 300

002024 056 003

002026 302

002027 207

002030 340

002031 060

002032 301

002033 217

002034 350

002035 364

002036 337

002037 066 302

002041 056 003

002043 302

002044 207

002045 340

002046 060

002047 301

002050 217

002051 350

002052 364

002053 373

002054 104 007 004

002057

</pre>

; MEMCPY --

; Copy a block of memory from one location to another.

;

; Entry parameters

; SRC: 14-bit address of source data block

; DST: 14-bit address of target data block

; CNT: 14-bit count of bytes to copy

ORG 1700Q ;Data at 001700q

SRC DFB 0 ;SRC, low byte

DFB 0 ; high byte

DST DFB 0 ;DST, low byte

DFB 0 ; high byte

CNT DFB 0 ;CNT, low byte

DFB 0 ; high byte

ORG 2000Q ;Code at 002000q

MEMCPY LLI CNT AND 255 ;HL = addr(CNT)

LHI CNT SHR 8 ;(AND and SHR not supported)

LCM ;BC = CNT

INL

LBM

LOOP LAC ;If BC = 0,

ORB

RTZ ;Return

DECCNT LAC ;BC = BC - 1

SUI 1

LCA

LAB

SBI 0

LBA

GETSRC LLI SRC AND 255 ;HL = addr(SRC)

LHI SRC SHR 8

LAC ;HL = SRC + BC

ADM ;E = C + (HL)

LEA ;(lower sum)

INL ;point to upper SRC

LAB

ACM ;H = B + (HL) + CY

LHA ;(upper sum)

LLE ;L = E

LDM ;Load D from (HL)

GETDST LLI DST AND 255 ;HL = addr(DST)

LHI DST SHR 8

LAC ;HL = DST + BC

ADM ;ADD code same as above

LEA

INL

LAB

ACM

LHA

LLE

LMD ;Store D to (HL)

JMP LOOP ;Repeat the loop

END

</syntaxhighlight>

In the code above, all values are given in octal. Locations , , and are 16-bit parameters for the subroutine named . In actuality, only 14 bits of the values are used, since the CPU has only a 14-bit addressable memory space. The values are stored in little-endian format, although this is an arbitrary choice, since the CPU is incapable of reading or writing more than a single byte into memory at a time. Since there is no instruction to load a register directly from a given memory address, the HL register pair must first be loaded with the address, and the target register can then be loaded from the M operand, which is an indirect load from the memory location in the HL register pair. The BC register pair is loaded with the parameter value and decremented at the end of the loop until it becomes zero. Note that most of the instructions used occupy a single 8-bit opcode.

Code example 2

The following 8008 assembly source code is for a simplified subroutine named MEMCPY2 that copies a block of data bytes from one location to another. By reducing the byte counter to 8 bits, there is enough room to load all the subroutine parameters into the 8008's register file.

<pre>

002000 307

002001 206 015 004

002004 370

002005 206 015 004

002010 021

002011 110 000 004

002014 007

002015 316

002016 364

002017 341

002020 315

002021 353

002022 331

002023 040

002024 013

002025 030

002026 007

002027

</pre>

; MEMCPY2 --

; Copy a block of memory from one location to another

;

; Entry parameters in registers

; HL: 14-bit address of source data block

; DE: 14-bit address of target data block

; C: 8-bit count of bytes to copy. (1 to 256 bytes)

ORG 2000Q ;Code at 002000q

MEMCPY2 LAM ;Read source byte into A

CAL XCHGI ;Exchange HL<->DE and increment DE

LMA ;Save A to target byte

CAL XCHGI ;Exchange HL<->DE and increment DE

DCC ;Decrement byte counter

JFZ MEMCPY2 ;Continue for all bytes

RET

;Exchange DE and HL register pairs then increment DE as 16 bits

XCHGI LBL ;Exchange L and E

LLE

LEB

LBH ;Exchange H and D

LHD

LDB

INE ;Inc E, low byte of DE

RFZ ;Return if no carry

IND ;Otherwise inc high byte D

RET

END

</syntaxhighlight>

Interrupts

thumb|Intel SIM8-01 CPU board, possibly the first use of the 8008. Contains 1K bytes of RAM in 32 chips and 2K bytes of EPROM in eight chips. No provision for interrupts.

Interrupts on the 8008 are only partially implemented. After the INT line is asserted, the 8008 acknowledges the interrupt by outputting a state code of S0,S1,S2 = 011 at T1I time. At the subsequent instruction fetch cycle, an instruction is "jammed" (Intel's word) by external hardware on the bus. Typically this is a one-byte RST instruction.

At this point, there is a problem. The 8008 has no provision to save its architectural state. The 8008 can only write to memory via an address in the HL register pair. When interrupted, there is no mechanism to save HL so there is no way to save the other registers and flags via HL. Because of this, some sort of external memory device such as a hardware stack or a pair of read/write registers must be attached to the 8008 via the I/O ports to help save the state of the 8008.

Designers

CTC (Instruction set and architecture): Victor Poor and Harry Pyle.
Intel (Implementation in silicon):
Ted Hoff and Stan Mazor proposed a single-chip implementation of the CTC architecture, using RAM-register memory rather than shift-register memory, and also added a few instructions and interrupt facility. The 8008 (originally called 1201) chip design started before the 4004 development. Hoff and Mazor, however, could not and did not develop a "silicon design" because they were neither chip designers nor process developers, and furthermore the necessary bootstrap load silicon-gate-based design methodology and circuits, under development by Federico Faggin for the 4004, were not yet available.
Federico Faggin, having finished the design of the 4004, became leader of the project from January 1971 until its successful completion in April 1972, after it had been suspended – for lack of progress – for about seven months.
Hal Feeney, project engineer, did the detailed logic design, circuit design, and physical layout under Faggin's supervision, employing the same design methodology that Faggin had originally developed for the Intel 4004 microprocessor, and utilizing the basic circuits he had developed for the 4004. A combined "HF" logo was etched onto the chip about halfway between the D5 and D6 bonding pads.

Second sources

image:KL MME U808.jpg|VEB Mikroelektronik "Karl Marx" Erfurt (MME) U808 (GDR)

image:KL MF8008.jpg|MicroSystems International (MIL) MF8008

image:Siemens SAB8008 1C 1.jpg|Siemens SAB8008

</gallery>

Notes

References

External links

MCS-8 User Manual with 8008 data sheet (1972)
The Intel 8008 support page unofficial
8008 Assembly Language Reference Card

History

Features

Instruction set

Code example 1

Code example 2

Interrupts

Designers

Second sources

See also

Notes

References

External links