Intel 4040

The Intel 4040 ("forty-forty") is the second 4-bit microprocessor designed and manufactured by Intel. Introduced in 1974 as a successor to the Intel 4004, the 4040 was produced with a 10 μm process and includes silicon gate enhancement-load PMOS logic technology. The 4040 contained 3,000 transistors

Interrupt handler code normally starts by saving out values in the registers to allow the interrupt code to use them, and then at the end it copies the values back from memory so that the processor returns to its original pre-interrupt state. With the multi-cycle memory access of the design, this would have been extremely slow. To address this, eight additional registers were added in a new "bank 1", the original sixteen registers retroactively becoming "bank 0". When an interrupt was received, the handler code would call an instruction to swap banks, which would cause bank 1's registers to override bank 0's registers 0 through 7. The handler code would then use these first eight registers for any local data, leaving the original values untouched. When the handler completed, it simply swapped bank 0 back in. This reduced the switching time to a single instruction, greatly improving interrupt response times.

Another addition was the input stop pin, and the associated output stop acknowledge. These could be used to stop the processor while the system performed input/output or other non-CPU tasks, but was more widely used for debugging by allowing the processor to be single-stepped. When the processor was in stopped mode, most of the chip hardware put into a low-drain, high-impedance condition, reducing power use. The machine cycle clocks were kept running for the benefit of external devices, including any interrupt controllers needed to wake the chip back up, which relied on these controllers staying in sync.

To take advantage of these new features, and to support the new logical <code>AND</code> and <code>OR</code> operators, the instruction set added 14 new instructions, bringing the total to 60.

{| class="infobox" style="font-size:88%;width:25em;"

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|+ Intel 4040 registers

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| style="width:10px; text-align:center;"| ¹₂

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| style="width:10px; text-align:center;"| ¹₀

| style="width:10px; text-align:center;"| ⁰₉

| style="width:10px; text-align:center;"| ⁰₈

| style="width:10px; text-align:center;"| ⁰₇

| style="width:10px; text-align:center;"| ⁰₆

| style="width:10px; text-align:center;"| ⁰₅

| style="width:10px; text-align:center;"| ⁰₄

| style="width:10px; text-align:center;"| ⁰₃

| style="width:10px; text-align:center;"| ⁰₂

| style="width:10px; text-align:center;"| ⁰₁

| style="width:10px; text-align:center;"| ⁰₀

| style="width:auto;" | (bit position)

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|colspan="14" | Accumulator

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| style="text-align:center; background:white" colspan="5"|

| style="text-align:center; background:white" colspan="4"|

| style="text-align:center;" colspan="4"| A

| style="width:auto; background:white; color:black;"| Accumulator

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|colspan="14" | Index registers

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R0

| style="text-align:center;" colspan="4"| R1

| style="width:auto; background:white; color:black;"| Index bank 0

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R2

| style="text-align:center;" colspan="4"| R3

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R4

| style="text-align:center;" colspan="4"| R5

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R6

| style="text-align:center;" colspan="4"| R7

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R8

| style="text-align:center;" colspan="4"| R9

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R10

| style="text-align:center;" colspan="4"| R11

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R12

| style="text-align:center;" colspan="4"| R13

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R14

| style="text-align:center;" colspan="4"| R15

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R0

| style="text-align:center;" colspan="4"| R1

| style="width:auto; background:white; color:black;"| Index bank 1

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R2

| style="text-align:center;" colspan="4"| R3

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R4

| style="text-align:center;" colspan="4"| R5

| style="width:auto; background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="4"| R6

| style="text-align:center;" colspan="4"| R7

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|colspan="14" | Program counter

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| style="text-align:center;" colspan="13"| PC

| style="background:white; color:black;"| Program Counter

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|colspan="14" | Push-down address call stack

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| PC1

| style="background:white; color:black;"| Call level 1

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| PC2

| style="background:white; color:black;"| Call level 2

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| PC3

| style="background:white; color:black;"| Call level 3

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| PC4

| style="background:white; color:black;"| Call level 4

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| PC5

| style="background:white; color:black;"| Call level 5

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| PC6

| style="background:white; color:black;"| Call level 6

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| PC7

| style="background:white; color:black;"| Call level 7

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|colspan="14" | Condition codes

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="12" |

| style="text-align:center;"| C

| style="background:white; color:black" | Carry flag

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Characteristics

• Data bus: 4-bit
• Address bus: 12-bit for ROM (multiplexed onto data bus; addresses took three bus cycles to transmit, same as in the 4004), effectively 13-bit with use of bank-switching commands; effectively 10-bit or 8-bit for RAM (8-bit direct address plus one-of-four, i.e. 2-bit equivalent, bank select; the additional 256 "status" memory locations required use of I/O commands to read or write, from an overall 8-bit address space)
• Voltage: −15 V DC
• Operating frequency: 500 to 740&nbsp;kHz main clock (2-phase, overlapping); 62500 to 92500 8-clock machine cycles per second, each instruction requiring either one or two machine cycles to read and execute, meaning a rough average of 62&nbsp;kIPS at 740&nbsp;kHz with an equal mix.
• Performance: Claimed execution time of ~850&nbsp;μs to add two 32-bit (8-digit BCD) numbers, or around 1175 such operations per second and about 10 machine cycles per digit pair.

Designers

Federico Faggin proposed the project, formulated the architecture and led the design. The detailed design was done by Tom Innes. The original mask show next to Tom Innes‘ initials (TI) two further initials from sofar unidentified other designers (JO, EL).

New support chips

• 3216 and 3226 4-bit parallel bus drivers
• 4101 – 256 × 4-bit Static RAM
• 4201 – Clock Generator, 500 to 740&nbsp;kHz, using 4.000 to 5.185&nbsp;MHz crystals
• 4207 – General Purpose 8-bit Output port
• 4209 – General Purpose 8-bit Input port
• 4211 – General Purpose 8-bit I/O port
• 4265 - Programmable general-purpose I/O. It contains four 4-bit I/O ports. It has 14 software-selectable modes that can be programmed to interface with these ports. Not only can the 4265 interface with the 4040, it can interface with the 8080A processor as well. It was available in sample quantities in stock in March 1976.
• 4269 – Programmable keyboard/display. It has system software configuration in this chipset via instructions that controls how these ports can be handled. It was available in sample quantities in March 1976.
• Keyboard Features: It generates an interrupt when the key is pressed. It stores up to 8 characters FIFO buffer prior servicing the CPU. It can be interfaced with sensors, panel switches and keyboards which it supports full teletypewriter size. That can be key input encoding, polling, character input buffer storage, and keyboard over-entry recovery.
• Display Features: It operates and refresh displays or indicator arrays up to 128 elements or lights. It also drives up to 20 gas-discharge characters on a display such as a Burroughs Self-Scan.
• 4289 – Standard Memory Interface (replaces 4008/4009)
• 4308 – 1K × 8-bit ROM plus 4 × 4-bit IO ports
• 4316 – 2K × 8-bit ROM
• 4702 – 256 × 8-bit EPROM

Use in computers

The 4040 was first used in a microcomputer in Intel's Intellec 4 Mod 40 development system, released in early 1975. According to Byte magazine, the first third-party microcomputer designed around the Intel 4040 was the Micro 440, released by Comp-Sultants of Huntsville, Alabama, in late 1975.

See also

• Intel Intellec 4 Mod 40

Notes

References

Further reading

<!-- these should really be cites for various of the above, but at least one of them would have to be tossed in about every other line -->

• ChipDB Datasheets: i4040 (PDF)
• Bitsavers: MCS-40 Users Manual, November 1974 (PDF)
• Pastraiser: i4040 Memory Organisation
• Wikichip: MCS-40
• CPU Zone: MCS-4 chipset
• CPU Zone: i4702