Hardware register

thumb|Internal structure of a basic n-bit register. The associated register-level block diagram symbol is shown on the right.

In digital electronics, a register is a group of memory cells that store a collection of bits and continuously output the stored data. It typically consists of a synchronized group of flip-flops in which each flip-flop stores and outputs one bit of the collection. The number of bits a register can store, known as its word size, is equal to the number of flip-flops it contains. Typically, the flip-flops also share a common reset input, which is used to initialize the stored data.

Moto MC74HCT374A die mit5x.jpg|Semiconductor die of an 8-bit register (Motorola MC74HCT374A)

TI SN74S374N.jpg|Assembled 8-bit register in a plastic dual-in-line package (Texas Instruments SN74S374N)

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Signal visibility

Depending on its implementation and purpose, a register's data inputs and outputs may all be public (accessible to external circuitry), or some data inputs or outputs (or both) may be designated for internal use only. An example of the latter is a serial-in serial-out shift register, which exposes only one data input and one data output to external circuitry.

Applications

In many applications, combinational logic is used to control when and how new data is stored in a register.

Load enable

In many applications, it is required to load (store new data in) a register only during specific clock cycles and to hold (retain currently stored data) during other clock cycles. This is facilitated by adding a "load enable" function to the register, which consists of logic gates and an associated control input — typically called clock enable (CE), load enable or simply load (LD) — that allows or inhibits loading depending on its state.

A simple way to implement this is to gate the register's clock input with the control signal, but this interferes with system timing because it introduces propagation delay into the clock's signal path. In general, it is not required for every address in the range to be assigned to a register, and a register may be assigned multiple addresses in the range.

The registers in a group typically share a data input bus for write operations, or a data output bus for read operations, or both. In the latter case, depending on the application, a register group may use separate buses for read and write operations or a single bus for both.

Write operation

In a write operation, a register is selected by sending its address to a binary decoder, which in turn enables the register to store new data. The register's data inputs are connected to and thus receive the data to be stored from a shared bus, as shown in the example circuit below.

File:Addressable register write.jpg|During a register write operation, write enable (WR) is asserted and the target register's address (ADDR) is sent to a binary decoder, which then asserts the register's load enable input (LD). Upon clock active edge, the selected register will store the word presented on the shared bus (DATA).

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Read operation

The process of reading an addressable register involves gating its output data onto a shared bus. Depending on the application, the gating mechanism may employ multiplexers or tri-state buffers, or both. The outputs of all registers in a group are accessible to the gating mechanism, thus allowing any register's output word to be sent to the bus. Some applications employ multiple instances of this mechanism to allow different registers (or a single register) to be concurrently gated onto multiple buses; each such instance is commonly called a read port. The AND gate prevents a flip-flop clear if a new request arrives while the previous request is being acknowledged, thus ensuring that new requests will not be missed. When both PEND and INTEN (interrupt enable) are active, a service request (IRQ) is sent to the interrupt controller.