thumb|400x400px|Figure 1: Full process of a first-order synchronous ΔΣ [[Analog-to-digital converter|ADC (top) and ΔΣ DAC (bottom). Each contains a ΔΣ modulation negative feedback loop (the curly bracket) which outputs a new <span style="font-family:Noto Sans;">ΔΣM</span> result on each clock cycle, which is fed back for computing the next <span style="font-family:Noto Sans;">ΔΣM</span> result. The full conversion process for each typically includes post-filtering for demodulation and pre-filtering to remove aliases and noise. Analog is green. Digital is blue. The DDC (Digital-to-Digital Converter) requantizes its input from a high bit depth to a low bit depth. ]]
thumb|330x330px|1-bit synchronous delta-sigma modulation (blue) of a sine wave (red)
Delta-sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is an oversampling method for encoding signals into low bit depth digital signals at a very high sample-frequency as part of the process of delta-sigma analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Delta-sigma modulation achieves high quality by utilizing a negative feedback loop during quantization to the lower bit depth that continuously corrects quantization errors and moves quantization noise to higher frequencies well above the original signal's bandwidth. Subsequent low-pass filtering for demodulation easily removes this high frequency noise and time averages to achieve high accuracy in amplitude, which can be ultimately encoded as pulse-code modulation (PCM).
Both ADCs and DACs can employ delta-sigma modulation. A delta-sigma ADC (e.g., Figure 1 top) encodes an analog signal using high-frequency delta-sigma modulation and then applies a digital filter to demodulate it to a high-bit digital output at a lower sampling frequency. A delta-sigma DAC (e.g., Figure 1 bottom) encodes a high-resolution digital input signal into a lower-resolution, but higher sample-frequency signal that may then be mapped to voltages and smoothed with an analog filter for demodulation. In both cases, the temporary use of a low bit depth signal at a higher sampling frequency simplifies circuit design and takes advantage of the efficiency and high accuracy in time of digital electronics.
Primarily because of its cost efficiency and reduced circuit complexity, this technique has found increasing use in modern electronic components such as DACs, ADCs, frequency synthesizers, switched-mode power supplies and motor controllers. The coarsely-quantized output of a delta-sigma ADC is occasionally used directly in signal processing or as a representation for signal storage (e.g., Super Audio CD stores the raw output of a 1-bit delta-sigma modulator).
While this article focuses on synchronous modulation, which requires a precise clock for quantization, asynchronous delta-sigma modulation instead runs without a clock.
Motivation
When transmitting an analog signal directly, all noise in the system and transmission is added to the analog signal, reducing its quality. Digitizing it enables noise-free transmission, storage, and processing. There are many methods of digitization.
In Nyquist-rate ADCs, an analog signal is sampled at a relatively low sampling frequency just above its Nyquist rate (twice the signal's highest frequency) and quantized by a multi-level quantizer to produce a multi-bit digital signal. Such higher-bit methods seek accuracy in amplitude directly, but require extremely precise components and so may suffer from poor linearity.
Advantages of oversampling
Oversampling converters instead produce a lower bit depth result at a much higher sampling frequency. This can achieve comparable quality by taking advantage of:
- Higher accuracy in time (afforded by high-speed digital circuits and highly accurate clocks).
- Higher linearity afforded by low-bit ADCs and DACs (for instance, a 1-bit DAC that only outputs two values of a precise high voltage and a precise low voltage is perfectly linear, in principle).
- Noise shaping: moving noise to higher frequencies above the signal of interest, so they can be easily removed with low-pass filtering.
- Reduced steepness requirement for the analog low-pass anti-aliasing filters. High-order filters with a flat passband cost more to make in the analog domain than in the digital domain.
Frequency/resolution tradeoff
Another key aspect given by oversampling is the frequency/resolution tradeoff. The decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the sampling rate, and hence the representable frequency range, of the signal, while increasing the sample amplitude resolution. This improvement in amplitude resolution is obtained by a sort of averaging of the higher-data-rate bitstream.
Improvement over delta modulation
Delta modulation is an earlier related low-bit oversampling method that also uses negative feedback, but only encodes the derivative of the signal (its delta) rather than its amplitude. The result is a stream of marks and spaces representing up or down movement of the signal, which must be integrated to reconstruct the signal's amplitude. Delta modulation has several drawbacks. The differentiation alters the signal's spectrum by amplifying high-frequency noise, attenuating low-frequencies,
Delta-sigma modulation rearranges the integrator and quantizer of a delta modulator so that the output carries information corresponding to the amplitude of the input signal instead of just its derivative. This also has the benefit of incorporating desirable noise shaping into the conversion process, to deliberately move quantization noise to frequencies higher than the signal. Since the accumulated error signal is low-pass filtered by the delta-sigma modulator's integrator before being quantized, the subsequent negative feedback of its quantized result effectively subtracts the low-frequency components of the quantization noise while leaving the higher frequency components of the noise.
1-bit delta-sigma modulation is pulse-density modulation
In the specific case of a single-bit synchronous ΔΣ ADC, an analog voltage signal is effectively converted into a pulse frequency, or pulse density, which can be understood as pulse-density modulation (PDM). A sequence of positive and negative pulses, representing bits at a known fixed rate, is very easy to generate, transmit, and accurately regenerate at the receiver, given only that the timing and sign of the pulses can be recovered. Given such a sequence of pulses from a delta-sigma modulator, the original waveform can be reconstructed with adequate precision.
The use of PDM as a signal representation is an alternative to PCM. Alternatively, the high-frequency PDM can later be downsampled through decimation and requantized to convert it into a multi-bit PCM code at a lower sampling frequency closer to the Nyquist rate of the frequency band of interest.
History and variations
The seminal paper combining feedback with oversampling to achieve delta modulation was by F. de Jager of Philips Research Laboratories in 1952.
thumb|"Feedback Integrating System" by Charles B Brahm: The entire top half of its Fig 1 is a delta-sigma modulator. Box #10 is a two-input [[integrator. The 4-bit analog-to-digital quantizer uses designations "S" (sign), "1", "2", and "4" for each bit. Each "F" stands for flip-flop and each "G" is a gate, controlled by the 110 kHz oscillator.]]
The principle of improving the resolution of a coarse quantizer by use of feedback, which is the basic principle of delta-sigma conversion, was first described in a 1954-filed patent by C. Chapin Cutler of Bell Labs. It was not named as such until a 1962 paper However, Charles B Brahm of United Aircraft Corp in 1961 filed a patent "Feedback integrating system" with a feedback loop containing an integrator with multi-bit quantization shown in its Fig 1.
Wooley's "The Evolution of Oversampling Analog-to-Digital Converters" Higher bit quantizers inherently produce less quantization noise.
One criticism of 1-bit quantization is that adequate amounts of dither cannot be used in the feedback loop, so distortion can be heard under some conditions (more discussion at ). Many of the issues of 1-bit modulation can be treated by look-ahead sigma-delta modulation.
Subsequent decimation
Decimation is strongly associated with delta-sigma modulation, but is distinct and outside the scope of this article. The original 1962 paper didn't describe decimation. Oversampled data in the early days was sent as is. The proposal to decimate oversampled delta-sigma data using digital filtering before converting it into PCM audio was made by D. J. Goodman at Bell Labs in 1969, to reduce the ΔΣ signal from its high sampling rate while increasing its bit depth. Decimation may be done in a separate chip on the receiving end of the delta-sigma bit stream, sometimes by a dedicated module inside of a microcontroller, which is useful for interfacing with PDM MEMS microphones, though many ΔΣ ADC integrated circuits include decimation. Some microcontrollers even incorporate both the modulator and decimator.
Decimation filters most commonly used for ΔΣ ADCs, in order of increasing complexity and quality, are:
- Boxcar moving average filter (simple moving average or sinc-in-frequency or sinc filter): This is the easiest digital filter and retains a sharp step response, but is mediocre at separating frequency bands and suffers from intermodulation distortion. The filter can be implemented by simply counting how many samples during a larger sampling interval are high. The 1974 paper from another Bell Labs researcher, J. C. Candy, "A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters" was one of the early examples of this.
- Cascaded integrator–comb filters: These are called sinc filters, equivalent to cascading the above sinc filter N times and rearranging the order of operations for computational efficiency. Lower N filters are simpler, settle faster, and have less attenuation in the baseband, while higher N filters are slightly more complex and settle slower and have more droop in the passband, but better attenuate undesired high-frequency noise. Compensation filters can, however, be applied to counteract undesired passband attenuation. Sinc filters are appropriate for decimating sigma delta modulation down to four times the Nyquist rate. The height of the first sideload is -13·N dB and the height of successive lobes fall off gradually, but only the areas around the nulls will alias into the low frequency band of interest; for instance when downsampling by 8, the largest aliased high frequency component may be -16 dB below the peak of the band of interest with a sinc filter but -40 dB below for a sinc filter, and if only interested in a narrower bandwidth, even fewer high frequency components will alias into it (see Figures 7–9 of Lyons article).
- Windowed sinc-in-time (brick-wall in frequency) filters: Although the sinc function's infinite support prevents it from being realizable in finite time, the sinc function can instead be windowed to realize finite impulse response filters. This approximated filter design, while maintaining almost no attenuation of the lower-frequency band of interest, still removes almost all undesired high-frequency noise. The downside is poor performance in the time domain (e.g. step response overshoot and ripple), higher delay (i.e. their convolution time is inversely proportional to their cutoff transition steepness), and higher computational requirements. They are the de facto standard for high fidelity digital audio converters.
Other loop filters
Most commercial ΔΣ modulators use integrators as the loop filter, because, as low-pass filters, they push quantization noise up in frequency, which is useful for baseband signals. But a ΔΣ modulator's filter does not necessarily need to be a low-pass filter. If a band-pass filter is used instead, then quantization noise is moved up and down in frequency away from the filter's pass-band, so a subsequent pass-band decimation filter will result in a ΔΣ ADC with a bandpass characteristic.
Reduction of baseband noise by increasing oversampling ratio and ΔΣM order
thumb|Figure 3: Top: a sine wave input overlaid with its synchronous ΔΣ representation made using a high oversampling ratio. Middle: filtering the ΔΣ representation produces an approximation of the original sine wave. Bottom: residual error of the ΔΣ ADC, with and without adding [[dither noise.|319x319px]]
When a signal is quantized, the resulting signal can be approximated by the addition of white noise with approximately equal intensity across the entire spectrum. In reality, the quantization noise is, of course, not independent of the signal and this dependence results in limit cycles and is the source of idle tones and pattern noise in delta-sigma converters. However, adding dithering noise (Figure 3) reduces such distortion by making quantization noise more random.
ΔΣ ADCs reduce the amount of this noise in the baseband by spreading it out and shaping it so it is mostly in higher frequencies. It can then be easily filtered out with inexpensive digital filters, without high-precision analog circuits needed by Nyquist ADCs.
Oversampling to spread out quantization noise
Quantization noise in the baseband frequency range (from DC to <math>2f_0</math>) may be reduced by increasing the oversampling ratio (OSR) defined by
:<math>\mathrm{OSR}\,=\,\frac{f_s}{2f_0} = 2^d</math>
where <math>f_\mathrm{s}</math> is the sampling frequency and <math>2f_0</math> is the Nyquist rate (the minimum sampling rate needed to avoid aliasing, which is twice the original signal's maximum frequency <math>f_0</math>). Since oversampling is typically done in powers of two, <math>d</math> represents how many times OSR is doubled.
thumb|320px|right|Figure 4: Noise shaping curves and noise spectrum in first-, second-, and third-order ΔΣ modulators.
As illustrated in Figure 4, the total amount of quantization noise is the same both in a Nyquist converter (yellow + green areas) and in an oversampling converter (blue + green areas). But oversampling converters distribute that noise over a much wider frequency range. The benefit is that the total amount of noise in the frequency band of interest is dramatically smaller for oversampling converters (just the small green area), than for a Nyquist converter (yellow + green total area).
Noise shaping
Figure 4 shows how ΔΣ modulation shapes noise to further reduce the amount of quantization noise in the baseband in exchange for increasing noise at higher frequencies (where it can be easily filtered out). The curves of higher-order ΔΣ modulators achieve even greater reduction of noise in the baseband.
These curves are derived using mathematical tools called the Laplace transform (for continuous-time signals, e.g., in an ADC's modulation loop) or the Z-transform (for discrete-time signals, e.g. in a DAC's modulation loop). These transforms are useful for converting harder math from the time domain into simpler math in the complex frequency domain of the complex variable <math>\text{s} = \sigma + j \omega</math> (in the Laplace domain) or <math>\text{z} = A e^{j\phi}</math> (in the z-domain).
Analysis of ΔΣ ADC modulation loop in Laplace domain
Figure 5 represents the first-order ΔΣ ADC modulation loop (from Figure 1) as a continuous-time linear time-invariant system in the Laplace domain with the equation:
thumb|Figure 5: ΔΣ modulation loop in Laplace domain. Integration is multiplication by <math>\tfrac{1}\text{s}</math> and quantization is approximated by adding noise.|270x270px
<math display="block">[ \text{in} (\text{s}) - \Delta \Sigma \text{M} (\text{s}) ] \cdot \frac{1}{\text{s + \text{noise} (\text{s}) = \Delta \Sigma \text{M} (\text{s}) \, .</math>
The Laplace transform of integration of a function of time corresponds to simply multiplication by <math>\tfrac{1}\text{s}</math> in Laplace notation. The integrator is assumed to be an ideal integrator to keep the math simple, but a real integrator (or similar filter) may have a more complicated expression.
The process of quantization is approximated as addition with a quantization error noise source. The noise is often assumed to be white and independent of the signal, though as explains, that is not always a valid assumption (particularly for low-bit quantization).
Since the system and Laplace transform are linear, the total behavior of this system can be analyzed by separating how it affects the input from how it affects the noise: also analyzes a ΔΣ ADC's modulation loop in the z-domain, which implicitly treats the continuous analog input as a discrete-time signal. This may be a valid approximation provided that the input signal is already bandlimited and can be assumed to be not changing on time scales higher than the sampling rate. It is particularly appropriate when the modulator is implemented as a switched capacitor circuit, which works by transferring charge between capacitors in clocked time steps.
thumb|265x265px|Figure 6: ΔΣ modulation loop in the z-domain.
Integration in discrete-time can be an accumulator which repeatedly sums its input <math>x[n]</math> with the previous result of its summation <math>y[n] = x[n] + y[n-1].</math> This is represented in the z-domain by feeding back a summing node's output <math>y(\text{z})</math> though a 1-clock cycle delay stage (notated as <math>\text{z}^\text{-1}</math>) into another input of the summing node, yielding Its transfer function <math>\tfrac{1}{1-\text{z}^\text{-1</math> is often used to label integrators in block diagrams.
In a ΔΣ DAC, the quantizer may be called a requantizer or a digital-to-digital converter (DDC), because its input is already digital and quantized but is simply reducing from a higher bit depth to a lower bit depth digital signal. This is represented in the z-domain by another <math>\text{z}^\text{-1}</math> delay stage in series with adding quantization noise. (Note: some sources may have swapped the ordering of the <math>\text{z}^\text{-1}</math> and additive noise stages.)
The modulator's z-domain equation arranged like Figure 6 is:<math display="block">[\text{in}(\text{z}) - \Delta\Sigma\text{M}(\text{z})] \cdot \frac{1}{1-\text{z}^\text{-1 \cdot \text{z}^\text{-1} + \text{noise}(\text{z}) = \Delta\Sigma\text{M}(\text{z}) \, ,</math>which can be rearranged to express the output in terms of the input and noise:<math display="block">\Delta\Sigma\text{M}(\text{z}) = \text{in}(\text{z}) \cdot \text{z}^\text{-1} + \text{noise}(\text{z}) \cdot (1 - \text{z}^\text{-1}) \, .</math>The input simply comes out of the system delayed by one clock cycle. The noise term's multiplication by <math>(1 - \text{z}^\text{-1})</math> represents a first difference backward filter (which has a single pole at the origin and a single zero at <math>\text{z}{=}1</math>) and thus high-pass filters the noise.
Higher order modulators
Without getting into the mathematical details,
<math display="block">\text{SNR}_\text{dB} \approx 3.01 \cdot (2 \cdot \Theta + 1) \cdot d - 9.36 \cdot \Theta - 2.76 \, .</math>The theoretical effective number of bits (ENOB) resolution is thus improved by <math display="inline">\Theta + \tfrac{1}{2}</math> bits when doubling the OSR (incrementing <math>d</math>), and by <math display="inline">d - \tfrac{3}{2}</math> bits when incrementing the order. For comparison, oversampling a Nyquist ADC (without any noise shaping) only improves its ENOB by <math>\tfrac{1}{2}</math> bits for every doubling of the OSR, which is only of the ENOB growth rate of a first-order ΔΣM.
{| class="wikitable"
|+Theoretical SNR and ENOB versus delta-sigma modulation order and oversampling ratio (OSR)
! rowspan="2" |
! colspan="5" |Oversampling ratio
! rowspan="2" |each OSR
doubling
|-
!2 OSR
!2 OSR
!2 OSR
!2 OSR
!2 OSR
|-
|
| dB
bits
| dB
bits
| dB
bits
| dB
bits
| dB
bits
| + bits
|-
|
| dB
bits
| dB
bits
| dB
bits
| dB
bits
| dB
bits
| + bits
|-
|
| dB
bits
| dB
bits
| dB
bits
| dB
bits
| dB
bits
| + bits
|-
|
| dB
bits
| dB
bits
| dB
bits
| dB
bits
| dB
bits
| + bits
|-
|
| dB
bits
| dB
19 bits
| dB
bits
| dB
30 bits
| dB
bits
| + bits
|-
|
| dB
16 bits
| dB
bits
| dB
29 bits
| dB
bits
| dB
42 bits
| + bits
|-
|
| + bits
| + bits
| + bits
| + bits
| + bits
|
|}
These datapoints are theoretical. In practice, circuits inevitably experience other noise sources that limit resolution, making the higher-resolution cells impractical.
Relationship to delta modulation
thumb|500px|right|Figure 7: Derivation of delta-sigma from [[delta modulation]]
Delta-sigma modulation is related to delta modulation by the following steps (Figure 7):
For simplicity, the D flip-flop is powered by dual supply voltages of V<sub>DD</sub> = +1 V and V<sub>SS</sub> = -1 V, so its binary output is either +1 V or -1 V.
2-input inverting integrator
The 2-input inverting op amp integrator combines with to produce :<math display="block"> \varepsilon(t) = -\frac{1}{RC}\int (s(t) + Q(t)) dt .</math>The Greek letter epsilon is used because contains the accumulated error that is repeatedly corrected by the feedback mechanism. While both its inputs and vary between -1 and 1 volts, instead only varies by a couple millivolts about 0 V.
Because of the integrator's negative sign, when next gets sampled to produce , the + in this integral actually represents negative feedback from the previous clock cycle.
Quantizer and sampler flip-flop
An ideal D flip-flop samples at the clock rate of 1 MHz. The scope view (Figure 8b) has a minor division equal to the sampling period of 1 μs, so every minor division corresponds to a sampling event. Since the flip-flop is assumed to be ideal, it treats any input voltage greater than 0 V as logical high and any input voltage smaller than 0 V as logical low, no matter how close it is to 0 V (ignoring issues of sample-and-hold time violations and metastability).
Whenever a sampling event occurs:
- if is above the 0 V threshold, then will go high (+1 V), or
- if is below the 0 V threshold, then will go low (-1 V).
is sent out as the resulting PDM output and also fed back to the 2-input inverting integrator.
Demodulation
The rightmost integrator performs digital-to-analog conversion on to produce a demodulated analog output , which reconstructs the original sine wave input as piece-wise linear diagonal segments. Although appears coarse at this 50x oversampling rate, can be low-pass filtered to isolate the original signal. As the sampling rate is increased relative to the input signal's maximum frequency, will more closely approximate the original input .
Digital-to-analog conversion
It is worth noting that if no decimation ever took place, the digital representation from a 1-bit delta-sigma modulator is simply a PDM signal, which can easily be converted to analog using a low-pass filter, as simple as a resistor and capacitor. structure has a steeper noise shaping property, so is commonly used in digital audio. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise-shaping function, it has two more attractive properties:
- simple to implement in hardware; only common digital blocks such as accumulators, adders, and D flip-flops are required
- unconditionally stable (there are no feedback loops outside the accumulators)
Naming
The technique was first presented in the early 1960s by professor Yasuhiko Yasuda while he was a student at the University of Tokyo. The name delta-sigma comes directly from the presence of a delta modulator and an integrator, as firstly introduced by Inose et al. in their patent application. That is, the name comes from integrating or summing differences, which, in mathematics, are operations usually associated with Greek letters sigma and delta respectively.
In the 1970s, Bell Labs engineers used the terms sigma-delta because the precedent was to name variations on delta modulation with adjectives preceding delta, and an Analog Devices magazine editor justified in 1990 that the functional hierarchy is sigma-delta, because it computes the integral of a difference.
Both names sigma-delta and delta-sigma are frequently used.
Asynchronous delta-sigma modulation
thumb|350x350px|Figure 9: 1-bit asynchronous ΔΣ modulation produces a PWM output (blue in bottom plot) which is subtracted from the input signal (green in top plot) to form an error signal (blue in top plot). This error is integrated (magenta in middle plot). When the integral of the error exceeds the limits (the upper and lower grey lines in middle plot), the PWM output changes state.
Kikkert and Miller published a continuous-time variant called Asynchronous Delta Sigma Modulation (ADSM or ASDM) in 1975, which uses either a Schmitt trigger (i.e. a comparator with hysteresis) or (as the paper argues is equivalent) a comparator with fixed delay.
In the example in Figure 9, when the integral of the error exceeds its limits, the output changes state, producing a pulse-width modulated (PWM) output wave.
Amplitude information is converted, without quantization noise, into time information of the output PWM. To convert this continuous time PWM to discrete time, the PWM may be sampled by a time-to-digital converter, whose limited resolution adds noise which can be shaped by feeding it back.
See also
- Pulse-width modulation
- Continuously variable slope delta modulation
- Class-D amplifier (sometimes