Datapoint 2200

The Datapoint 2200 was a mass-produced programmable terminal usable as a computer, designed by Computer Terminal Corporation (CTC) founders Phil Ray and Gus Roche and announced by CTC in June 1970 (with units shipping in 1971). It was initially presented by CTC as a versatile and cost-efficient terminal for connecting to a wide variety of mainframes by loading various terminal emulations from tape rather than being hardwired as most contemporary terminals, including their earlier Datapoint 3300.

Dave Gust, a CTC salesman, realized that the 2200 could meet Pillsbury Foods's need for a small computer in the field, after which the 2200 was marketed as a stand-alone computer.

The terminal's multi-chip CPU (processor) instruction set became the basis of the Intel 8008 instruction set, which inspired the Intel 8080 instruction set and the x86 instruction set used in the processors for the original IBM PC and its descendants.

Technical description

{| class="infobox" style="font-size:88%;width:30em;"

|+ Datapoint 2200 version I registers

|-

| style="text-align:center;"| ¹₂

| style="text-align:center;"| ¹₁

| style="text-align:center;"| ¹₀

| style="text-align:center;"| ⁰₉

| style="text-align:center;"| ⁰₈

| style="text-align:center;"| ⁰₇

| style="text-align:center;"| ⁰₆

| style="text-align:center;"| ⁰₅

| style="text-align:center;"| ⁰₄

| style="text-align:center;"| ⁰₃

| style="text-align:center;"| ⁰₂

| style="text-align:center;"| ⁰₁

| style="text-align:center;"| ⁰₀

| (bit position)

|-

|colspan="15" | Main registers

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="8"| A

| style="width:auto; background:white; color:black;"| Accumulator

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="8"| B

| style="background:white; color:black;"| B register

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="8"| C

| style="background:white; color:black;"| C register

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="8"| D

| style="background:white; color:black;"| D register

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="8"| E

| style="background:white; color:black;"| E register

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="8"| H

| style="background:white; color:black;"| H register (indirect)

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="5"|

| style="text-align:center;" colspan="8"| L

| style="background:white; color:black;"| L register (indirect)

|-

|colspan="15" | Program counter

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| P

| style="background:white; color:black;"| Program Counter

|-

|colspan="15" | 15-level push-down address stack

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| AS

| style="background:white; color:black;"| Call level 1

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| AS

| style="background:white; color:black;"| Call level 2

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| AS

| style="background:white; color:black;"| Call level 3

|-

| style="text-align:center;" colspan="13"| ...

| style="background:white; color:black;"|

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| AS

| style="background:white; color:black;"| Call level 13

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| AS

| style="background:white; color:black;"| Call level 14

|- style="background:silver;color:black"

| style="text-align:center;" colspan="13"| AS

| style="background:white; color:black;"| Call level 15

|-

|colspan="15" | Flags

|- style="background:silver;color:black"

| style="text-align:center; background:white" colspan="9" |

| style="text-align:center;"| C

| style="text-align:center;"| P

| style="text-align:center;"| Z

| style="text-align:center;"| S

| style="background:white; color:black" | Flags

|}

The Datapoint 2200 had a built-in full-travel keyboard, a built-in 12-line, 80-column green screen monitor, and two 47 character-per-inch cassette tape drives each with 130 KB capacity. Its size, , and shape—a box with protruding keyboard—approximated that of an IBM Selectric typewriter.

The 2200 models were succeeded by the 5500, 1100, 6600, 3800/1800, 8800, etc.

The fact that most laptops and cloud computers today store numbers in little-endian format is carried forward from the original Datapoint 2200. Because the original Datapoint 2200 had a serial processor, it needed to start with the lowest bit of the lowest byte in order to handle carries. Microprocessors descended from the Datapoint 2200 (the 8008, Z80, and the x86 chips used in most laptops and cloud computers today) kept the little-endian format used by that original Datapoint 2200.

Processor

The original design called for a single-chip 8-bit microprocessor for the CPU, rather than a processor built from discrete TTL modules as was conventional at the time. In 1969, CTC contracted two companies, Intel and Texas Instruments (TI), to make the chip. TI was unable to make a reliable part and dropped out. Intel was unable to make CTC's deadline. Intel and CTC renegotiated their contract, ending up with CTC keeping its money and Intel keeping the eventually completed processor.

Possibly because of their speed advantages compared to MOS circuits, Datapoint continued to build processors out of TTL chips until the early 1980s.

Nonetheless, the 8008 was to have a seminal importance. It was the basis of Intel's line of 8-bit CPUs, which was followed by their assembly language compatible 16-bit CPUs — the first members of the x86 family, as the instruction set was later to be known. Already successful and widely used, the x86 architecture's further rise after the success in 1981 of the original IBM Personal Computer with an Intel 8088 CPU means that most desktop, laptop, and server computers in use have a CPU instruction set directly based on the work of CTC's engineers. The instruction set of the highly successful Zilog Z80 microprocessor can also be traced back to the Datapoint 2200 as the Z80 was backwards-compatible with the Intel 8080. More immediately, the Intel 8008 was adopted by very early microcomputers including the SCELBI, Mark-8, MCM/70 and Micral N.

Instruction set

Instructions are one to three bytes long, consisting of an initial opcode byte, followed by up to two bytes of operands which can be an immediate operand or a program address. Instructions operate on 8-bits only; there are no 16-bit operations. There is only one mechanism to address data memory: indirect addressing pointed to by a concatenation of the H and L registers, referenced as M. The 2200 does, however, support 13-bit program addresses. It has automatic CALL and RETURN instructions for multi-level subroutine calls and returns which can be conditionally executed, like jumps. Direct copying may be made between any two registers or a register and memory. Eight math/logic functions are supported between the accumulator (A) and any register, memory, or an immediate value. Results are always deposited in A. Most instructions are executed in 16 μs, 24 μs, or a leisurely 520 μs when accessing M. The 520 μs represents the delay of the 2200's shift register memory to fully recirculate back to the next instruction. Branch type instructions take a variable amount of time (24 μs to 520 μs) depending on the distance of the branch.

{|class="wikitable" style="text-align:center"

|+Datapoint 2200 version I instruction set

!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Time μs ||rowspan=2| Description

|-

! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3

|-

| 0 || 0 || 0 || 0 || 0 || 0 || 0 || X || — || — ||align=left| HALT || — ||align=left| Halt

|-

| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || — || — ||align=left| SLC || 16 ||align=left| A_1-7 ← A_0-6; A₀ ← Cy ← A₇

|-

| 0 || 0 ||colspan=3|CC || 0 || 1 || 1 || — || — ||align=left| Rcc (RETURN conditional) || 16/† ||align=left| If cc true, P ← (stack)

|-

| 0 || 0 ||colspan=3|ALU || 1 || 0 || 0 || data || — ||align=left| AD AC SU SB ND XR OR CP data || 16 ||align=left| A ← A [ALU operation] data

|-

| 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || data || — ||align=left| Lr data (Load r with immediate data) || 16 ||align=left| DDD ← data (except M)

|-

| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || — || — ||align=left| RETURN || † ||align=left| P ← (stack)

|-

| 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || — || — ||align=left| SRC || 16 ||align=left| A_0-6 ← A_1-7; A₇ ← Cy ← A₀

|-

| 0 || 1 ||colspan=3|CC || 0 || 0 || 0 || addlo || addhi ||align=left| Jcc add (JMP conditional) || 24/† ||align=left| If cc true, P ← add

|-

| 0 || 1 || 0 || 0 || 0 || 0 || 0 || 1 || — || — ||align=left| INPUT || 16 ||align=left| A ← input

|-

| 0 || 1 ||colspan=5|command || 1 || — || — ||align=left| EX command (external command)|| 16 ||align=left| command ← A (coded 8-31 only)

|-

| 0 || 1 ||colspan=3|CC || 0 || 1 || 0 || addlo || addhi ||align=left| Ccc add (CALL conditional) || 24/† ||align=left| If cc true, (stack) ← P, P ← add

|-

| 0 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || addlo || addhi ||align=left| JMP add || † ||align=left| P ← add

|-

| 0 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || addlo || addhi ||align=left| CALL add || † ||align=left| (stack) ← P, P ← add

|-

| 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || — || — ||align=left| ADr ACr SUr SBr NDr XRr ORr CPr || 16/520 ||align=left| A ← A [ALU operation] SSS

|-

| 1 || 1 || 0 || 0 || 0 || 0 || 0 || 0 || — || — ||align=left| NOP || 16 ||align=left| No operation (Actually LAA)

|-

| 1 || 1 ||colspan=3|DDD ||colspan=3|SSS || — || — ||align=left| Lds (Load d with s) ||16/520 ||align=left| DDD ← SSS

|-

| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 || — || — ||align=left| HALT || — ||align=left| Halt

|-

! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Time μs || Description

|-

!colspan=13|

|-

!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU

|-

|colspan=5| A || 0 || 0 || 0 ||colspan=2|FC, C false ||align=left|ADr AD (A ← A + arg)||colspan=2|† Variable. Can be from 24 μs to 520 μs.

|-

|colspan=5| B || 0 || 0 || 1||colspan=2|FZ, Z false||align=left|ACr AC (A ← A + arg + Cy)

|-

|colspan=5| C || 0 || 1 || 0||colspan=2|FS, S false ||align=left|SUr SU (A ← A - arg)

|-

|colspan=5| D || 0 || 1 || 1||colspan=2|FP, P odd ||align=left|SBr SB (A ← A - arg - Cy)

|-

|colspan=5| E || 1 || 0 || 0||colspan=2|TC, C true ||align=left|NDr ND (A ← A ∧ arg)

|-

|colspan=5| H || 1 || 0 || 1||colspan=2|TZ, Z true ||align=left|XRr XR (A ← A ⊻ arg)

|-

|colspan=5| L || 1 || 1 || 0||colspan=2|TS, S true ||align=left|ORr OR (A ← A ∨ arg)

|-

|colspan=5| M || 1 || 1 || 1||colspan=2|TP, P even ||align=left|CPr CP (A - arg)

|-

!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU

|}

Performance

Although the Datapoint 2200 version I is somewhat faster than an Intel 8008 on register instructions, any reference to the 2200's shift-register memory incurs a large 520 μs delay. Also any JMP, CALL, or RETURN can incur a variable delay up to 520 μs depending on the distance to the new address. The parallel-architecture Datapoint 2200 version II is much faster than either.

{|class="wikitable" style="text-align:center"

|-

!colspan=5|Instruction|| Description || Datapoint 2200 ver I μs|| 500 kHz Intel 8008 μs|| Datapoint 2200 ver II μs

|-

|colspan=5|ADB|| Add B to A || 16 || 20 || 3.2

|-

|colspan=5|ADI nn|| Add nn immediate to A || 16 || 32 || 4.8

|-

|colspan=5|ADM|| Add memory to A || 520 || 32 || 4.8

|-

|colspan=5|JMP nnnn|| Jump to nnnn || 24-520 || 44 || 6.4

|-

|colspan=5|CALL+RET|| Call and Ret combined|| 520 || 64 || 9.6

|-

|colspan=5|Rcc (false)|| Conditional return not taken || 16 || 12 || 3.2

|}

Code example

The following Datapoint 2200 assembly source code is for a subroutine named MEMCPY that copies a block of data bytes from one location to another. Because the byte counter is only 8 bits, there is enough room to load all the subroutine parameters into the 2200's register file. Datapoint 2200 version I transfers 374 bytes per second using this routine. A 500 kHz Intel 8008 executes this code almost four times faster, transferring 1,479 bytes per second. Datapoint 2200 version II is much faster than either at 9,615 bytes per second. The TTL design they ended up using was made by Gary Asbell. Industrial design (how the box's exterior looked, including the company's logo) was done by Jack Frassanito.