DIMM - WikiHQ

thumb|Two types of DIMMs: a 168-pin [[SDRAM module (top) and a 184-pin DDR SDRAM module (bottom). The SDRAM module has two notches (rectangular cuts or incisions) on the bottom edge, while the DDR1 SDRAM module has one. Also, each module has eight RAM chips, but the lower one has an unoccupied space for the ninth chip; this space is occupied in ECC DIMMs.]]

thumb|upright=1.6|Three [[SDRAM DIMM slots on a ABIT BP6 computer motherboard.]]

A DIMM (Dual In-line Memory Module) is a type of memory module used in computers. It is a printed circuit board with one or both sides (front and back) holding DRAM chips and pins. The vast majority of DIMMs are manufactured in compliance with JEDEC memory standards, although there are proprietary DIMMs. DIMMs come in a variety of speeds and capacities, and are generally one of two lengths: PC, which are , and laptop (SO-DIMM), which are about half the length at .. The first known DIMM was developed by James Testa, Andreas Bechtolsheim, Edward Frank, Trevor Creary, David Emberson, Shawn Storm, and Bradley Hoffert at Sun Microsystems for the SparcStation 10, released in 1992 (referred to as a "dual-readout SIMM in US Patent No. 5,265,218 issued November 23, 1993). In 1995, JEDEC introduced the 198-pin DIMM standard, adopted by Intel as the Intel P5-based Pentium processors began to gain market share. The Pentium had a 64-bit bus width, which would require 32-bit memory modules installed in matched pairs in order to populate the data bus. The processor would then access the two 32-bit SIMM modules in parallel. The name "DIMM" was chosen as an acronym for Dual In-line Memory Module symbolizing the split in the contacts of a SIMM into two independent rows. This allowed them to double the SIMMs 32-bit data path into a 64-bit data path.

Form factors

Widths

DIMMs come in a number of board sizes. In order of descending size: DIMM, SO-DIMM, MiniDIMM, and MicroDIMM.

Regular DIMMs are generally 133.35 mm in length, while SO-DIMMs are generally 67.6 mm in length.

File:Nanonote 03 2.jpg|256 MB MicroDIMM PC133 SDRAM (double sided, 4 chips).

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SO-DIMM

thumb|Assorted SO-DIMM Modules

thumb|A DDR SO-DIMM slot on a computer [[motherboard.]]

A SO-DIMM (pronounced "so dim" , also spelled SODIMM) or small outline DIMM, is a smaller alternative to a DIMM, being roughly half the physical size of a regular DIMM. The first SO-DIMMs had 72 pins and were introduced by JEDEC in 1997. Before its introduction, many laptops would use proprietary RAM modules which were expensive and hard to find.

SO-DIMMs are often used in computers that have limited space, which include laptops, notebook computers, small-footprint personal computers such as those based on Nano-ITX motherboards, high-end upgradable office printers, and networking hardware such as routers and NAS devices. They are usually available with the same size data path and speed ratings of the regular DIMMs though normally with smaller capacities.

File:THL32V1055BTG-6.jpg|The original 72-pin SO-DIMM

File:IBM_SO-DIMM_ram_128mb.jpg|SO-DIMM SDR 144pin 128MB ram chip by IBM

File:Samsung-1GB-DDR2-Laptop-RAM.jpg|A 200-pin PC2-5300 DDR2 SO-DIMM.

File:4GB_DDR3_SO-DIMM.jpg|A 204-pin PC3-10600 DDR3 SO-DIMM.

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Connector

thumb|A comparison between 200-pin DDR and DDR2 SDRAM SO-DIMMs, and a 204-pin DDR3 SO-DIMM module. They share the same width but differ in pin and notch placement.

thumb|16 GiB DDR4-2666 1.2 V [[UDIMM|unbuffered DIMM (UDIMM).]]

Different generations of memory are not interchangable: neither forward compatible nor backward compatible. To make this difference clear and avoid any confusion, their DIMM modules all have different pin counts and/or different notch positions. DDR5 SDRAM is the most recent type of DDR memory and has been in use since 2020.

;DIMM

:* 100-pin: printer SDRAM and printer ROM (e.g., PostScript)

:* 168-pin: SDR SDRAM, sometimes used for FPM/EDO DRAM in workstations or servers, may be 3.3 or 5 V

:* 184-pin: DDR SDRAM

:* 200-pin: FPM/EDO DRAM in some Sun workstations and servers

:* 240-pin: DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM

:* 278-pin: HP high density SDRAM

:* 288-pin: DDR4 SDRAM and DDR5 SDRAM

;SO-DIMM

:* 72-pin: FPM DRAM and EDO DRAM; different pin configuration from 72-pin SIMM

:* 144-pin: SDR SDRAM,

{|class=wikitable

|+JEDEC standard heights for DIMMs

! rowspan=2|Generation !! colspan=2|Full-height (1U) !! colspan=2|Very low profile (VLP) !! rowspan=2 |Notes

! Nominal !! Maximum !! Nominal !! Maximum

! DDR2

| || || || ||

! DDR3

| || || || ||

! DDR4

| || || || ||

! DDR5

| || || ||

For DIMMs, there is a new height called 2U DIMM at nominal and max.
DDR5 and LPDDR5 also use CAMM2 units. These are mounted flush to the motherboard.

Notes:

Low profile (LP) is not a JEDEC standard.
The full JEDEC standards also regulate factors such as thickness.
SO-DIMMs for DDR4 and DDR5 maintain the traditional height of  mm; see JEDEC MO-310A and MO-337B. The height increase for "full height" DIMM does not apply to SO-DIMM.
It is common for higher-end consumer DDR4 DIMMs to exceed the JEDEC full height due to the use of an added heat sink. Some heat sinks add as little as while others add up to .

Similar connectors

As of Q2 2017, Asus has had a PCIe based "DIMM.2", which has a similar socket to DDR3 DIMMs and is used to put in a module to connect up to two M.2 NVMe solid-state drives. However, it cannot use common DDR type ram and does not have much support from other than Asus.

Components

Organization

Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with up to nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in bits. High-capacity DIMMs such as 256 GB DIMMs can have up to 19 chips per side.

In the case of "×4" registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked. For "×8" registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked).

The above example applies to ECC memory that stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight, which is not counted.

Ranking

Sometimes, memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a rank. Of the ranks that share the same memory slot, i.e. on the same module, only one rank may be accessed at any given time. The rank to be accessed is specified by activating its chip select (CS) signal, while the other ranks on the same module are deactivated for the duration of the operation by having their corresponding CS signals deactivated.

After a memory word is fetched, the memory is typically inaccessible for an extended period of time while the sense amplifiers are charged for access of the next cell. These amplifiers typically have 3 cycles of idle time for recharging between accesses. By interleaving the memory (e.g. cells 0, 4, 8, ... are stored in one rank, cells 1, 5, 9, ... in another rank, and so on), sequential memory accesses can be performed more rapidly by alternating which rank is active, thus overlapping the active memory access with recharge time for the inactive ranks.

, DIMMs are commonly manufactured with one, two, or four ranks per module. Consumer DIMM vendors have begun to distinguish between single- and dual-ranked DIMMs since around 2020.

DIMMs are often referred to as "single-sided" or "double-sided" to describe whether the DRAM chips are located on one or both sides of the module's printed circuit board (PCB). However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed. Indeed, quad-ranked DIMMs exist.

JEDEC decided that the terms "dual-sided", "double-sided", or "dual-banked" were not correct when applied to registered DIMMs (RDIMMs).

Multiplexed Rank DIMM (MRDIMM) allow data from multiple ranks to be transmitted on the same channel. It was announced for DDR5 in July 2024 and is expected to be backwards compatible with DDR5 RDIMM.

SPD EEPROM

A DIMM's capacity and other operational parameters may be identified with serial presence detect (SPD), an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. The SPD EEPROM connects to the System Management Bus and may also contain thermal sensors (TS-on-DIMM).

Features

Speeds

For various technologies, there are certain bus and device clock frequencies that are standardized; there is also a decided nomenclature for each of these speeds for each type.

DIMMs based on Single Data Rate (SDR) DRAM have the same bus frequency for data, address and control lines. DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock; this is achieved by clocking on both the rising and falling edge of the data strobes. Power consumption and voltage gradually became lower with each generation of DDR-based DIMMs.

Another influence is Column Access Strobe (CAS) latency, or CL, which affects memory access speed. This is the delay time between the READ command and the moment data is available. See main article CAS/CL and memory timing.

{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"

|+ SDR SDRAM DIMMs

! scope="col" | Chip

! scope="col" | Module

! scope="col" | Effective clock ()

! scope="col" | Transfer rate (Transfers per second|)

! scope="col" | Voltage (Volt|)

! scope="row" | SDR-66

| PC-66 || 66 || 66 || 3.3

! scope="row" | SDR-100

| PC-100 || 100 || 100|| 3.3

! scope="row" | SDR-133

| PC-133 || 133 || 133 || 3.3

{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"

|+ DDR SDRAM (DDR1) DIMMs

! scope="col" | Chip

! scope="col" | Module

! scope="col" | Memory clock ()

! scope="col" | I/O bus clock ()

! scope="col" | Transfer rate (Transfers per second|)

! scope="col" | Voltage (Volt|)

! scope="row" | DDR-200

| PC-1600 || 100 || 100 || 200 || 2.5

! scope="row" | DDR-266

| PC-2100 || 133 || 133 || 266 || 2.5

! scope="row" | DDR-333

| PC-2700 || 166 || 166 || 333 || 2.5

! scope="row" | DDR-400

| PC-3200 || 200 || 200 || 400 || 2.6

{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"

|+ DDR2 SDRAM DIMMs

! scope="col" | Chip

! scope="col" | Module

! scope="col" | Memory clock ()

! scope="col" | I/O bus clock ()

! scope="col" | Transfer rate (Transfers per second|)

! scope="col" | Voltage (Volt|)

! scope="row" | DDR2-400

| PC2-3200 || 100 || 200 || 400 || 1.8

! scope="row" | DDR2-533

| PC2-4200 || 133 || 266 || 533 || 1.8

! scope="row" | DDR2-667

| PC2-5300 || 166 || 333 || 667 || 1.8

! scope="row" | DDR2-800

| PC2-6400 || 200 || 400 || 800 || 1.8

! scope="row" |

| || 266 || 533 || 1066 || 1.8

{| class="wikitable plainrowheaders defaultright col1left col2left"

|+ DDR3 SDRAM DIMMs

! scope="col" | Chip

! scope="col" | Module

! scope="col" | Memory clock ()

! scope="col" | I/O bus clock ()

! scope="col" | Transfer rate (Transfers per second|)

! scope="col" | Voltage (Volt|)

! scope="row" | DDR3-800

| PC3-6400 || 100 || 400 || 800 || 1.5

! scope="row" | DDR3-1066

| PC3-8500 || 133 || 533 || 1066 || 1.5

! scope="row" | DDR3-1333

| PC3-10600 || 166 || 667 || 1333 || 1.5

! scope="row" | DDR3-1600

| PC3-12800 || 200 || 800 || 1600 || 1.5

! scope="row" | DDR3-1866

| PC3-14900 || 233 || 933 || 1866 || 1.5

! scope="row" | DDR3-2133

| PC3-17000 || 266 || 1066 || 2133 || 1.5

! scope="row" | DDR3-2400

| PC3-19200 || 300 || 1200 || 2400 || 1.5

{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"

|+ DDR4 SDRAM DIMMs

! scope="col" | Chip

! scope="col" | Module

! scope="col" | Memory clock ()

! scope="col" | I/O bus clock ()

! scope="col" | Transfer rate (Transfers per second|)

! scope="col" | Voltage (Volt|)

! scope="row" | DDR4-1600

| PC4-12800 || 200 || 800 || 1600 || 1.2

! scope="row" | DDR4-1866

| PC4-14900 || 233 || 933 || 1866 || 1.2

! scope="row" | DDR4-2133

| PC4-17000 || 266 || 1066 || 2133 || 1.2

! scope="row" | DDR4-2400

| PC4-19200 || 300 || 1200 || 2400 || 1.2

! scope="row" | DDR4-2666

| PC4-21300 || 333 || 1333 || 2666 || 1.2

! scope="row" | DDR4-3200

| PC4-25600 || 400 || 1600 || 3200 || 1.2

{| class="wikitable plainrowheaders defaultright col1left col2left" style="margin-right: 2em;"

|+ DDR5 SDRAM DIMMs

! scope="col" | Chip

! scope="col" | Module

! scope="col" | Memory clock ()

! scope="col" | I/O bus clock ()

! scope="col" | Transfer rate (Transfers per second|)

! scope="col" | Voltage (Volt|)

! scope="row" | DDR5-4000

| PC5-32000 || 2000 || 2000 || 4000 || 1.1

! scope="row" | DDR5-4400

| PC5-35200 || 2200 || 2200 || 4400 || 1.1

! scope="row" | DDR5-4800

| PC5-38400 || 2400 || 2400 || 4800 || 1.1

! scope="row" | DDR5-5200

| PC5-41600 || 2600 || 2600 || 5200 || 1.1

! scope="row" | DDR5-5600

| PC5-44800 || 2800 || 2800 || 5600 || 1.1

! scope="row" | DDR5-6000

| PC5-48000 || 3000 || 3000 || 6000 || 1.1

! scope="row" | DDR5-6200

| PC5-49600 || 3100 || 3100 || 6200 || 1.1

! scope="row" | DDR5-6400

| PC5-51200 || 3200 || 3200 || 6400 || 1.1

! scope="row" | DDR5-6800

| PC5-54400 || 3400 || 3400 || 6800 || 1.1

! scope="row" | DDR5-7200

| PC5-57600 || 3600 || 3600 || 7200 || 1.1

! scope="row" | DDR5-7600

| PC5-60800 || 3800 || 3800 || 7600 || 1.1

! scope="row" | DDR5-8000

| PC5-64000 || 4000 || 4000 || 8000 || 1.1

! scope="row" | DDR5-8400

| PC5-67200 || 4200 || 4200 || 8400 || 1.1

! scope="row" | DDR5-8800

| PC5-70400 || 4400 || 4400 || 8800 || 1.1

Error correction

ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect (SECDED) which uses an extra byte per 64-bit word. ECC modules usually carry a multiple of 9 instead of a multiple of 8 chips as a result.

Register/buffer

It is electrically demanding for a memory controller to drive many DIMMs. Registered DIMMs add a hardware register to the clock, address, and command lines so that the signals are refreshed on the DIMM, allowing a reduced load on the memory controller. Variants include LRDIMM with all lines buffered and CUDIMM/CSODIMM with only the clock signal buffered. The register feature often occurs with ECC, but they do not actually depend on each other and can occur independently.

References

External links

How to Install PC Memory guides
Very Low Profile (VLP) DDR2 Whitepaper (PDF)
Is 4GB RAM Good For a Laptop?

Form factors

Widths

SO-DIMM

Connector

Similar connectors

Components

Organization

Ranking

SPD EEPROM

Features

Speeds

Error correction

Register/buffer

See also

References

External links