Cell (processor)

The Cell Broadband Engine (Cell/B.E.) is a 64-bit reduced instruction set computer (RISC) multi-core processor and microarchitecture developed by Sony, Toshiba, and IBM—an alliance known as "STI". It combines a general-purpose PowerPC core, named the Power Processing Element (PPE), with multiple specialized coprocessors, known as Synergistic Processing Elements (SPEs), which accelerate tasks such as multimedia and vector processing.

The architecture was developed over a four-year period beginning in March 2001, with Sony reporting a development budget of approximately . Its first major commercial application was in Sony's PlayStation 3 home video game console, released in 2006. In 2008, a modified version of the Cell processor powered IBM's Roadrunner, the first supercomputer to sustain one petaFLOPS. Other applications include high-performance computing systems from Mercury Computer Systems and specialized arcade system boards.

Cell emphasizes memory coherence, power efficiency, and peak computational throughput, but its design presented significant challenges for software development. IBM offered a Linux-based software development kit to facilitate programming on the platform.

History

thumb|Cell BE as it appears in the PS3 on the motherboard

In mid-2000, Sony, Toshiba, and IBM formed the STI alliance to develop a new microprocessor. The STI Design Center opened in March 2001 in Austin, Texas. Over the next four years, more than 400 engineers collaborated on the project, with IBM contributing from eleven of its design centers.

Initial patents described a configuration with four Power Processing Elements (PPEs), each paired with eight Synergistic Processing Elements (SPEs), for a theoretical peak performance of 1 teraFLOPS. However, only a scaled-down design—one PPE with eight SPEs—was ultimately manufactured.

Fabrication of the initial Cell chip began on a 90 nm SOI (silicon on insulator) process. followed by a 45 nm process announced in February 2008. Bandai Namco Entertainment used the Cell processor in its Namco System 357 and 369 arcade boards.

In May 2008, IBM introduced the PowerXCell 8i, a double-precision variant of the Cell processor, used in systems such as IBM's Roadrunner supercomputer, the first to achieve one petaFLOPS and the fastest until late 2009.

IBM ceased development of higher-core-count Cell variants (such as a 32-APU version) in late 2009, but continued supporting existing Cell-based products.

Commercialization

On May 17, 2005, Sony confirmed the Cell configuration used in the PlayStation 3: one PPE and seven SPEs. To improve manufacturing yield, the processor is initially fabricated with eight SPEs. After production, each chip is tested, and if a defect is found in one SPE, it is disabled using laser trimming. This approach minimizes waste by utilizing processors that would otherwise be discarded. Even in chips without defects, one SPE is intentionally disabled to ensure consistency across units. Of the seven operational SPEs, six are available for developers to use in games and applications, while the seventh is reserved for the console's operating system. Sony also used the Cell in its Zego high-performance media computing server.

The PPE supports simultaneous multithreading (SMT) and can execute two threads, while each active SPE supports one thread. In the PlayStation 3 configuration, the Cell processor supports up to nine threads.

On June 28, 2005, IBM and Mercury Computer Systems announced a partnership to use Cell processors in embedded systems for medical imaging, aerospace, and seismic processing, among other fields. Mercury use the full Cell processor with eight active SPEs. Mercury later released blade servers and PCI Express accelerator cards based on the architecture.

In 2006, IBM introduced the QS20 blade server, offering up to 410 gigaFLOPS per module in single-precision performance. The QS22 blade, based on the PowerXCell 8i, was used in IBM's Roadrunner supercomputer.

Overview

The Cell Broadband Engine, or Cell as it is more commonly known, is a microprocessor intended as a hybrid of conventional desktop processors (such as the Athlon 64, and Core 2 families) and more specialized high-performance processors, such as the NVIDIA and ATI graphics-processors (GPUs). The longer name indicates its intended use, namely as a component in current and future online distribution systems; as such it may be utilized in high-definition displays and recording equipment, as well as HDTV systems. Additionally the processor may be suited to digital imaging systems (medical, scientific, etc.) and physical simulation (e.g., scientific and structural engineering modeling). As used in the PlayStation 3, it has 250 million transistors.

In a simple analysis, the Cell processor can be split into four components: external input and output structures, the main processor called the Power Processing Element (PPE) (a two-way simultaneous-multithreaded PowerPC 2.02 core), eight fully functional co-processors called the Synergistic Processing Elements, or SPEs, and a specialized high-bandwidth circular data bus connecting the PPE, input/output elements and the SPEs, called the Element Interconnect Bus or EIB.

To achieve the high performance needed for mathematically intensive tasks, such as decoding/encoding MPEG streams, generating or transforming three-dimensional data, or undertaking Fourier analysis of data, the Cell processor marries the SPEs and the PPE via EIB to give access, via fully cache coherent DMA (direct memory access), to both main memory and to other external data storage. To make the best of EIB, and to overlap computation and data transfer, each of the nine processing elements (PPE and SPEs) is equipped with a DMA engine. Since the SPE's load/store instructions can only access its own local scratchpad memory, each SPE entirely depends on DMAs to transfer data to and from the main memory and other SPEs' local memories. A DMA operation can transfer either a single block area of size up to 16KB or a list of 2 to 2048 such blocks. One of the major design decisions in the architecture of Cell is the use of DMAs as a central means of intra-chip data transfer, with a view to enabling maximal asynchrony and concurrency in data processing inside a chip.

The PPE, which is capable of running a conventional operating system, has control over the SPEs and can start, stop, interrupt, and schedule processes running on the SPEs. To this end, the PPE has additional instructions relating to the control of the SPEs. Unlike SPEs, the PPE can read and write the main memory and the local memories of SPEs through the standard load/store instructions. The SPEs are not fully autonomous and require the PPE to prime them before they can do any useful work. As most of the "horsepower" of the system comes from the synergistic processing elements, the use of DMA as a method of data transfer and the limited local memory footprint of each SPE pose a major challenge to software developers who wish to make the most of this horsepower, demanding careful hand-tuning of programs to extract maximal performance from this CPU.

The PPE and bus architecture includes various modes of operation, giving different levels of memory protection, allowing areas of memory to be protected from access by specific processes running on the SPEs or the PPE.

Both the PPE and SPE are RISC architectures with a fixed-width 32-bit instruction format. The PPE contains a 64-bit general-purpose register set (GPR), a 64-bit floating-point register set (FPR), and a 128-bit Altivec register set. The SPE contains 128-bit registers only. These can be used for scalar data types ranging from 8-bits to 64-bits in size, or for SIMD computations on various integer and floating-point formats. System memory addresses for both the PPE and SPE are expressed as 64-bit values. Local store addresses internal to the SPU (Synergistic Processor Unit) processor are expressed as a 32-bit word. In documentation relating to Cell, a "word" is always taken to mean 32 bits, a "doubleword" means 64 bits, and a "quadword" means 128 bits.

PowerXCell 8i

In 2008, IBM announced a revised variant of the Cell called the PowerXCell 8i, which is available in the blade server by IBM, QS22. The PowerXCell is manufactured on a 65 nm process, and adds support for up to 32 GB of slotted double data rate 2 memory, as well as dramatically improving double-precision floating-point performance on the SPEs from a peak of about 12.8 giga-floating point operations per second (GFLOPS) to 102.4 GFLOPS total for eight SPEs, which is the same peak performance as the NEC SX-9 vector processor released around the same time. The IBM Roadrunner supercomputer, the world's fastest during 2008–2009, consisted of 12,240 PowerXCell 8i processors, along with 6,562 AMD Opteron processors. The PowerXCell 8i powered supercomputers also dominated all of the top 6 "greenest" systems in the Green500 list, with highest MFLOPS/Watt ratio supercomputers in the world. Beside the QS22 and supercomputers, the PowerXCell processor is also available as an accelerator on a PCI Express card and is used as the core processor in the QPACE project.

Since the PowerXCell 8i removed the RAMBUS memory interface, and added significantly larger DDR2 interfaces and enhanced SPEs, the chip layout had to be reworked, which resulted in both larger chip die and packaging.

Architecture

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While the Cell chip can have a number of different configurations, the basic configuration is a multi-core chip composed of one "Power Processor Element" ("PPE") (sometimes called "Processing Element", or "PE"), and multiple "Synergistic Processing Elements" ("SPE"). The PPE and SPEs are linked together by an internal high speed bus dubbed "Element Interconnect Bus" ("EIB").

Power Processor Element (PPE)

thumb|PPE

The PPE is the PowerPC based, dual-issue in-order two-way simultaneous-multithreaded CPU core with a 23-stage pipeline acting as the controller for the eight SPEs, which handle most of the computational workload. PPE has limited out-of-order execution capabilities; it can perform loads out of order and has delayed execution pipelines. The PPE will work with conventional operating systems due to its similarity to other 64-bit PowerPC processors, while the SPEs are designed for vectorized floating point code execution. The PPE contains a 32 KiB level 1 instruction cache, a 32 KiB level 1 data cache, and a 512 KiB level 2 cache. The size of a cache line is 128 bytes in all caches. which is fully pipelined for single precision floating point (Altivec 1 does not support double precision floating-point vectors.), 32-bit Fixed Point Unit (FXU) with 64-bit register file per thread, Load and Store Unit (LSU), 64-bit Floating-Point Unit (FPU), Branch Unit (BRU) and Branch Execution Unit(BXU).

Xenon in Xbox 360

The PPE was designed specifically for the Cell processor, but during development, Microsoft approached IBM wanting a high-performance processor core for its Xbox 360. IBM complied and made the tri-core Xenon processor, based on a slightly modified version of the PPE with added VMX128 extensions.

Synergistic Processing Element (SPE)

thumb|SPE

Each SPE is a dual issue, in-order processor composed of a "Synergistic Processing Unit", SPU, and a "Memory Flow Controller", MFC (DMA, MMU, and bus interface). SPEs do not have any branch prediction hardware (hence there is a heavy burden on the compiler). Each SPE has 6 execution units divided among odd and even pipelines on each SPE: The SPU runs a specially developed instruction set (ISA) with 128-bit SIMD organization for single and double precision instructions. With the current generation of the Cell, each SPE contains a 256 KiB embedded SRAM for instruction and data, called "Local Storage" (not to be mistaken for "Local Memory" in Sony's documents that refer to the VRAM) which is visible to the PPE and can be addressed directly by software. Each SPE can support up to 4 GiB of local store memory. The local store does not operate like a conventional CPU cache since it is neither transparent to software nor does it contain hardware structures that predict which data to load. The SPEs contain a 128-bit, 128-entry register file and measures 14.5 mm<sup>2</sup> on a 90 nm process. An SPE can operate on sixteen 8-bit integers, eight 16-bit integers, four 32-bit integers, or four single-precision floating-point numbers in a single clock cycle, as well as a memory operation. Note that the SPU cannot directly access system memory; the 64-bit virtual memory addresses formed by the SPU must be passed from the SPU to the SPE memory flow controller (MFC) to set up a DMA operation within the system address space.

In one typical usage scenario, the system will load the SPEs with small programs (similar to threads), chaining the SPEs together to handle each step in a complex operation. For instance, a set-top box might load programs for reading a DVD, video and audio decoding, and display, and the data would be passed off from SPE to SPE until finally ending up on the TV. Another possibility is to partition the input data set and have several SPEs performing the same kind of operation in parallel. At 3.2 GHz, each SPE gives a theoretical 25.6 GFLOPS of single-precision performance.

Compared to its personal computer contemporaries, the relatively high overall floating-point performance of a Cell processor seemingly dwarfs the abilities of the SIMD unit in CPUs like the Pentium 4 and the Athlon 64. However, comparing only floating-point abilities of a system is a one-dimensional and application-specific metric. Unlike a Cell processor, such desktop CPUs are more suited to the general-purpose software usually run on personal computers. In addition to executing multiple instructions per clock, processors from Intel and AMD feature branch predictors. The Cell is designed to compensate for this with compiler assistance, in which prepare-to-branch instructions are created. For double-precision floating-point operations, as sometimes used in personal computers and often used in scientific computing, Cell performance drops by an order of magnitude, but still reaches 20.8 GFLOPS (1.8 GFLOPS per SPE, 6.4 GFLOPS per PPE). The PowerXCell 8i variant, which was specifically designed for double-precision, reaches 102.4 GFLOPS in double-precision calculations.

Tests by IBM show that the SPEs can reach 98% of their theoretical peak performance running optimized parallel matrix multiplication. In total, the SPEs have 2 MB of local memory.

Element Interconnect Bus (EIB)

The EIB is a communication bus internal to the Cell processor which connects the various on-chip system elements: the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces, for a total of 12 participants in the PS3 (the number of SPU can vary in industrial applications). The EIB also includes an arbitration unit, which functions as a set of traffic lights. In some documents, IBM refers to EIB participants as 'units'.

The EIB is presently implemented as a circular ring consisting of four 16-byte-wide unidirectional channels that counter-rotate in pairs. When traffic patterns permit, each channel can convey up to three transactions concurrently. As the EIB runs at half the system clock rate the effective channel rate is 16 bytes every two system clocks. At maximum concurrency, with three active transactions on each of the four rings, the peak instantaneous EIB bandwidth is 96 bytes per clock (12 concurrent transactions × 16 bytes wide / 2 system clocks per transfer). While this figure is often quoted in IBM literature, it is unrealistic to simply scale this number by processor clock speed. The arbitration unit imposes additional constraints.

IBM Senior Engineer David Krolak, EIB lead designer, explains the concurrency model:

Each participant on the EIB has one 16-byte read port and one 16-byte write port. The limit for a single participant is to read and write at a rate of 16 bytes per EIB clock (for simplicity often regarded 8 bytes per system clock). Each SPU processor contains a dedicated DMA management queue capable of scheduling long sequences of transactions to various endpoints without interfering with the SPU's ongoing computations; these DMA queues can be managed locally or remotely as well, providing additional flexibility in the control model.

Data flows on an EIB channel stepwise around the ring. Since there are twelve participants, the total number of steps around the channel back to the point of origin is twelve. Six steps is the longest distance between any pair of participants. An EIB channel is not permitted to convey data requiring more than six steps; such data must take the shorter route around the circle in the other direction. The number of steps involved in sending the packet has very little impact on transfer latency: the clock speed driving the steps is very fast relative to other considerations. However, longer communication distances are detrimental to the overall performance of the EIB as they reduce available concurrency.

Despite IBM's original desire to implement the EIB as a more powerful cross-bar, the circular configuration they adopted to spare resources rarely represents a limiting factor on the performance of the Cell chip as a whole. In the worst case, the programmer must take extra care to schedule communication patterns where the EIB is able to function at high concurrency levels.

David Krolak explained: