Asynchronous circuit

Asynchronous circuit (clockless or self-timed circuit) is a sequential digital logic circuit that does not use a global clock circuit or signal generator to synchronize its components. Instead, the components are driven by a handshaking circuit which indicates a completion of a set of instructions. Handshaking works by simple data transfer protocols. Many synchronous circuits were developed in early 1950s as part of bigger asynchronous systems (e.g. ORDVAC). Asynchronous circuits and theory surrounding is a part of several steps in integrated circuit design, a field of digital electronics engineering.

Asynchronous circuits are contrasted with synchronous circuits, in which changes to the signal values in the circuit are triggered by repetitive pulses called a clock signal. Most digital devices today use synchronous circuits. However asynchronous circuits have a potential to be much faster, have a lower level of power consumption, electromagnetic interference, and better modularity in large systems. Asynchronous circuits are an active area of research in digital logic design.

It was not until the 1990s when viability of the asynchronous circuits was shown by real-life commercial products.

Overview

All digital logic circuits can be divided into combinational logic, in which the output signals depend only on the current input signals, and sequential logic, in which the output depends both on current input and on past inputs. In other words, sequential logic is combinational logic with memory. Virtually all practical digital devices require sequential logic. Sequential logic can be divided into two types, synchronous logic and asynchronous logic.

Synchronous circuits

In synchronous logic circuits, an electronic oscillator generates a repetitive series of equally spaced pulses called the clock signal. The clock signal is supplied to all the components of the IC. Flip-flops only flip when triggered by the edge of the clock pulse, so changes to the logic signals throughout the circuit begin at the same time and at regular intervals. The output of all memory elements in a circuit is called the state of the circuit. The state of a synchronous circuit changes only on the clock pulse. The changes in signal require a certain amount of time to propagate through the combinational logic gates of the circuit. This time is called a propagation delay.

, timing of modern synchronous ICs takes significant engineering efforts and sophisticated design automation tools. Designers have to ensure that clock arrival is not faulty. With the ever-growing size and complexity of ICs (e.g. ASICs) it's a challenging task. This theory was presented later in the well-known book "Switching Theory" by Raymond Miller.

The term "asynchronous logic" is used to describe a variety of design styles, which use different assumptions about circuit properties. These vary from the bundled delay model – which uses "conventional" data processing elements with completion indicated by a locally generated delay model – to delay-insensitive design – where arbitrary delays through circuit elements can be accommodated. The latter style tends to yield circuits which are larger than bundled data implementations, but which are insensitive to layout and parametric variations and are thus "correct by design".

Asynchronous logic

Asynchronous logic is the logic required for the design of asynchronous digital systems. These function without a clock signal and so individual logic elements cannot be relied upon to have a discrete true/false state at any given time. Boolean (two valued) logic is inadequate for this and so extensions are required.

Since 1984, Vadim O. Vasyukevich developed an approach based upon new logical operations which he called venjunction (with asynchronous operator "x∠y" standing for "switching x on the background y" or "if x when y then") and sequention (with priority signs "xi≻xj" and "xi≺xj"). This takes into account not only the current value of an element, but also its history. and Tam-Anh Chu. Since then, STGs have been studied extensively in theory and practice, which has led to the development of popular software tools for analysis and synthesis of asynchronous control circuits, such as Petrify and Workcraft.

Subsequent to Petri nets other models of concurrency have been developed that can model asynchronous circuits including the Actor model and process calculi.

Benefits

A variety of advantages have been demonstrated by asynchronous circuits. Both quasi-delay-insensitive (QDI) circuits (generally agreed to be the most "pure" form of asynchronous logic that retains computational universality) and less pure forms of asynchronous circuitry which use timing constraints for higher performance and lower area and power present several advantages.

Robust and cheap handling of metastability of arbiters.
Average-case performance: an average-case time (delay) of operation is not limited to the worst-case completion time of component (gate, wire, block etc.) as it is in synchronous circuits. This results in better latency and throughput performance. Examples include speculative completion which has been applied to design parallel prefix adders faster than synchronous ones, and a high-performance double-precision floating point adder which outperforms leading synchronous designs.
Early completion: the output may be generated ahead of time, when result of input processing is predictable or irrelevant.
Inherent elasticity: variable number of data items may appear in pipeline inputs at any time (pipeline means a cascade of linked functional blocks). This contributes to high performance while gracefully handling variable input and output rates due to unclocked pipeline stages (functional blocks) delays (congestions may still be possible however and input-output gates delay should be also taken into account).
No need for timing-matching between functional blocks either. Though given different delay models (predictions of gate/wire delay times) this depends on actual approach of asynchronous circuit implementation.
Freedom from the ever-worsening difficulties of distributing a high-fan-out, timing-sensitive clock signal.
Circuit speed adapts to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.
Lower, on-demand power consumption; zero standby power consumption. In 2005 Epson has reported 70% lower power consumption compared to synchronous design. Also, clock drivers can be removed which can significantly reduce power consumption. However, when using certain encodings, asynchronous circuits may require more area, adding similar power overhead if the underlying process has poor leakage properties (for example, deep submicrometer processes used prior to the introduction of high-κ dielectrics).
No need for power-matching between local asynchronous functional domains of circuitry. Synchronous circuits tend to draw a large amount of current right at the clock edge and shortly thereafter. The number of nodes switching (and hence, the amount of current drawn) drops off rapidly after the clock edge, reaching zero just before the next clock edge. In an asynchronous circuit, the switching times of the nodes does not correlated in this manner, so the current draw tends to be more uniform and less bursty.
Robustness toward transistor-to-transistor variability in the manufacturing transfer process (which is one of the most serious problems facing the semiconductor industry as dies shrink), variations of voltage supply, temperature, and fabrication process parameters.
Less severe electromagnetic interference (EMI). Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.
Design modularity (reuse), improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations.

Disadvantages

Area overhead caused by additional logic implementing handshaking. In some cases an asynchronous design may require up to double the resources (area, circuit speed, power consumption) of a synchronous design, due to addition of completion detection and design-for-test circuits.
Compared to a synchronous design, as of the 1990s and early 2000s not many people are trained or experienced in the design of asynchronous circuits. However, this position is disputed by Fant, who claims that the apparent simplicity of synchronous logic is an artifact of the mathematical models used by the common design approaches.
Lack of dedicated, asynchronous design-focused commercial EDA tools. Making a clockless CPU (designing an asynchronous circuit) involves modifying the design tools to handle clockless logic and doing extra testing to ensure the design avoids metastable problems. The group that designed the AMULET, for example, developed a tool called LARD to cope with the complex design of AMULET3.

Examples

Despite all the difficulties numerous asynchronous CPUs have been built.

The ORDVAC of 1951 was a successor to the ENIAC and the first asynchronous computer ever built.

; Caltech Asynchronous Microprocessor (CAM)

In 1988 the Caltech Asynchronous Microprocessor (CAM) was the first asynchronous, quasi delay-insensitive (QDI) microprocessor made by Caltech. The processor had 16-bit wide RISC ISA and separate instruction and data memories. Synchronous flexible processors are slower, since bending the material on which a chip is fabricated causes wild and unpredictable variations in the delays of various transistors, for which worst-case scenarios must be assumed everywhere and everything must be clocked at worst-case speed. The processor is intended for use in smart cards, whose chips are currently limited in size to those small enough that they can remain perfectly rigid.

IBM

In 2014, IBM announced a SyNAPSE-developed chip that runs in an asynchronous manner, with one of the highest transistor counts of any chip ever produced. IBM's chip consumes orders of magnitude less power than traditional computing systems on pattern recognition benchmarks.

Timeline

ORDVAC and the (identical) ILLIAC I (1951)
Johnniac (1953)
WEIZAC (1955)
Kiev (1958), a Soviet machine using the programming language with pointers much earlier than they came to the PL/1 language
ILLIAC II (1962)
Polish computers KAR-65 and K-202 (1965 and 1970 respectively)
Honeywell CPUs 6180 (1972) and Series 60 Level 68 (1981) upon which Multics ran asynchronously

Soviet bit-slice microprocessor modules (late 1970s) produced as К587, К588 and К1883 (U83x in East Germany)
Caltech Asynchronous Microprocessor, the world-first asynchronous microprocessor (1988)
"Network-based Asynchronous Architecture" processor (2005) that executes a subset of the MIPS architecture instruction set
ARM996HS processor (2006) from Handshake Solutions
HT80C51 processor (2007?) from Handshake Solutions.
Vortex, a superscalar general purpose CPU with a load/store architecture from Intel (2007); it was developed as Fulcrum Microsystem test Chip 2 and was not commercialized, excepting some of its components; the chip included DDR SDRAM and a 10Gb Ethernet interface linked via Nexus system-on-chip net to the CPU
SEAforth multi-core processor (2008) from Charles H. Moore
GA144 multi-core processor (2010) from Charles H. Moore
TAM16: 16-bit asynchronous microcontroller IP core (Tiempo)
Aspida asynchronous DLX core; the asynchronous open-source DLX processor (ASPIDA) has been successfully implemented both in ASIC and FPGA versions

Asynchronous circuit

Overview

Synchronous circuits

Asynchronous logic

Benefits

Disadvantages

Examples

IBM

Timeline

See also

Notes

References

Further reading

External links